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Thermal Studies on Stress-Induced Void-Like Defects in Epitaxial-CoSi2 Formation

Published online by Cambridge University Press:  10 February 2011

C. S. Ho ,
K. L. Pey ,
C. H. Tung ,
K. C. Tee ,
K. Prasad ,
D. Saigal ,
Jackie J. L. Tan ,
H. Wong ,
K. H. Lee  and
T. Osipowicz
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C. S. Ho
Affiliation:
Dept of Electrical Engineering
K. L. Pey
Affiliation:
Dept of Electrical Engineering
C. H. Tung
Affiliation:
lnstitute of Microelectronics, Singapore;
K. C. Tee
Affiliation:
Microelectronics Characterization Lab, Nanyang Technological University, Singapore
K. Prasad
Affiliation:
Microelectronics Characterization Lab, Nanyang Technological University, Singapore
D. Saigal
Affiliation:
Applied Materials, MPD Division, Santa Clara, CA95054, USA, Singapore Office
Jackie J. L. Tan
Affiliation:
Applied Materials, MPD Division, Santa Clara, CA95054, USA, Singapore Office
H. Wong
Affiliation:
R&D Process Module, Chartered Semiconductor Manufacturing Ltd.. Singapore Now with Siliconix Inc.. Santa Clara, CA, USA
K. H. Lee
Affiliation:
R&D Process Module, Chartered Semiconductor Manufacturing Ltd.. Singapore
T. Osipowicz
Affiliation:
Dept. of Physics, National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260
S. J. Chua
Affiliation:
Dept of Electrical Engineering
R. P. G. Karunasiri
Affiliation:
Dept of Electrical Engineering
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Abstract

We report experimental findings on the thermal-induced stress-voiding observed during epitaxial CoSi2 formation on patterned Si(100) wafers associated with the Co/Ti-interposing layer scheme [1–6]. The first rapid thermal process (RTP) in a typical SALICIDE process was studied by varying the temperature and the RTP ramp-up rate. Based on ex-situ cross-sectional transmission electron microscopy (XTEM), crystal defects were observed at shallow trench isolation (STI)/Si and gate spacer/Si edges after annealing at temperatures greater than 520°C. In addition, isothermal anneals for various time periods resulted in increased encroachment of an ultra-thin CoSi2-phase at the STI/Si edge. Higher temperature anneals also resulted in a corresponding increase in void size. In addition, higher ramp-up rates led to a thicker CoSi2 “pocket” film at the tensile-stressed STI/Si edge, aligned epitaxially along the {111}-habit planes. Our attempts to bypass the CoSi formation in order to alleviate the anomalous Si diffusion was found to be irrelevant to the voiding issue, due to the inherent nature of this film stack system to nucleate CoSi2 as the first phase. By comparing our experimental observations of voiding with Hu's analysis of the trench isolation stress fields, we found good agreement with the predicted stress field distribution in the active Si and STI/Si edge with the locations of void nucleation. The anomalously large stress induced is still not known, but can be attributed to the encroaching CoSi2 film which tends to realign epitaxially along the STI/Si interface.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 564: Symposium N – Advanced Interconnects and Contacts , 1999 , 109
Copyright
Copyright © Materials Research Society 1999

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