Future CMOS technology nodes bring new challenges to formation of source/drain junctions and their contacts. To avoid MOSFET performance degradation with scaling, series resistance contribution of each junction must be limited to five percent of the device channel resistance. This requires ultra-shallow junctions with extremely low sheet, spreading and contact resistance. In this paper, we present an overview of the SiGe junction technology recently proposed by this laboratory for nanoscale CMOS. The technology is based on selective deposition of boron or phosphorus doped SiGe alloys in source/drain regions isotropically etched to the desired junction depth. Since the dopant atoms naturally occupy the substitutional sites during growth, the need for an activation anneal is completely eliminated limiting the maximum process temperature to 550°C for boron and 750°C for phosphorus. In this temperature range, dopant diffusion is virtually eliminated resulting in extremely abrupt doping profiles. Elimination of the high temperature implant anneal also makes the process compatible with the thermal stability needs of future high-K gate dielectrics. A key advantage of the technology is its potential to reduce the junction contact resistance. SiGe provides a smaller bandgap under the metal contact resulting in a smaller metal-semiconductor barrier height. Since the contact resistivity is an exponential function of the barrier height, the technology provides a significant advantage in reducing the contact resistivity. The results to date indicate that the technology is a promising alternative for nanoscale CMOS source/drain junctions and their contacts.