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Planarization of Copper Damascene Interconnects by Spin-Etch Process: A Chemical Approach

Published online by Cambridge University Press:  17 March 2011

Shyama P. Mukherjee ,
Joseph A. Levert  and
Donald S. Debear
Shyama P. Mukherjee
Affiliation:
Honeywell Electronic Materials, 1349 Moffett Park Dr., Sunnyvale, CA, USA
Joseph A. Levert
Affiliation:
Honeywell Electronic Materials, 1349 Moffett Park Dr., Sunnyvale, CA, USA
Donald S. Debear
Affiliation:
SEZ America Inc, 4824 South 40th St., Phoenix, AZ 85040, USA
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Abstract

The present work describes the process principles of “Spin-Etch Planarization” (SEP), an emerging method of planarization of dual damascene copper interconnects. The process involves a uniform removal of copper and the planarization of surface topography of copper interconnects by dispensing abrasive free etchants to a rotating wafer. The primary process parameters comprise of (a) Physics and chemistry of etchants, and (b) Nature of fluid flow on a spinning wafer. It is evident, that unlike conventional chemical-mechanical planarization, which has a large number of variables due to the presence of pads, normal load, and abrasives, SEP has a smaller number of process parameters and most of them are primary in nature. Based on our preliminary works, we have presented the basic technical parameters that contribute to the process and satisfy the basic requirements of planarization such as (a) Uniformity of removal (b) Removal rate (c) Degree of Planarization (d) Selectivity. The anticipated advantages and some inherent limitations are discussed in the context of process principles. We believe that when fully developed, SEP will be a simple, predictable and controllable process.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 612: Symposium D – Materials, Technology & Reliability for Advanced Interconnects.. , 2000 , E8.10.1
Copyright
Copyright © Materials Research Society 2000

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References

REFERENCES

1. Andricacos, P. C., Uzoh, C., Dukovic, J. O., Horkins, J., and Deligianni, H., IBM J. Res. Development 42 (5) 567–574 (1998).10.1147/rd.425.0567Google Scholar
2. Wrschka, P., Hernandez, J., Oehrlein, G. S. and King, J., J. Electrochemical Soc. 147 (2) 206–712 (2000).10.1149/1.1393256Google Scholar
3. Levert, J. A., Mukherjee, S. P., DeBear, D. S., Semicon Japan 99: SEMI Technology Symposium, 94-3 to 4-81 (1999).Google Scholar
4. DeBear, D. S., Levert, J. A., Mukherjee, S. P., Solid State Technology, March, 53–58.(2000).Google Scholar
5. Contolini, R. J., Mayer, S. T., Graf, R. T., Tarte, L., Bernhardt, A. F., Solid State Technology, June 155–158 ( 1997).Google Scholar
6. Bloor, J. W., J. Metals of Australia 4, 276–282 (1972).Google Scholar
7. Lysaght, P. S., and West, M., Solid State Technology, November 63–70 (1999).Google Scholar