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New Method to Characterize Thin Oxide Reliability

Published online by Cambridge University Press:  15 February 2011

Heng-Chih Lin ,
J. P. Snyder  and
C. R. Helms
Heng-Chih Lin
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
J. P. Snyder
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
C. R. Helms
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
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Abstract

Next generation ULSI devices will require ultra thin gate insulators where degradation due to contamination or surface microroughness is an even more important problem. Tunneling and breakdown characteristics are critical electrical testing methods, but unfortunately obtaining meaningful oxide integrity information on the one hand and tunneling IV's on the other is a tedious and time consuming process.

In this research, we report on a new method to measure meaningful IV's, Qbd's, and Vbd's at the same time. This method uses a linear current ramp strategy where a voltage ramp to between 8–10 MV/cm is applied first followed by a linear current ramp until breakdown is reached. There are several advantages of this new method: The linear voltage ramp quickly and easily identifies low breakdown devices, whereas switching to a linear current ramp provides for nearly constant field stressing to obtain meaningful IV and Qbd

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 386: Symposium O – Ultraclean Semiconductor Processing Technology and Surface , 1995 , 237
Copyright
Copyright © Materials Research Society 1995

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References

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