In 3D packaging, Through Silicon Vias (TSVs) with high aspect ratios and depths measuring tens of microns are filled by advanced Cu electroplating processes. Today's 300mm TSV plating platforms are intended to produce bottom-up via fill, no seam voids, and minimal, controlled overburden. To achieve this, the preceding Cu-seed coverage must be continuous at a constant resistance, and the plating chemistries optimized. However, other factors such as hardware configurations and simple depletion of the plating formulations during the extended TSV process can lead to high Cu overburden thickness requiring a high removal rate (HRR) chemical-mechanical polish (CMP) process to remove the thick Cu layer.

Presented here are CMP results of a thick Cu overburden (~6um) resulting from the fill of 5 x 25um TSVs on 300mm wafers. The goal is to uniformly polish the overburden and utilize the tool's endpoint system at Cu clear before the next step of conventional barrier CMP. Slurries were screened for removal rate, uniformity, planarization ability, and defectivity. This study focuses on achieving a removal rate of >2.5um/min through evaluation of several commercial slurries in a multi-step polish application. Cross-sections post-plating show the Cu overburden, barrier and liner layer. Cross-sections post-CMP quantify Cu recess, dielectric loss, and presence/absence of seam defects. The process selected is demonstrated to achieve good planarization results with low occurrence of polish defects, at a rate and selectivity suitable for emerging 3D TSV Cu CMP applications.