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Computer Simulation of Grain Growth in Thin-film Interconnect Lines

Published online by Cambridge University Press:  15 February 2011

D. T. Walton ,
H. J. Frost  and
C. V. Thompson
D. T. Walton
Affiliation:
Thayer School of Engineering, Dartmouth College, Hanover, N.H. 03755
H. J. Frost
Affiliation:
Thayer School of Engineering, Dartmouth College, Hanover, N.H. 03755
C. V. Thompson
Affiliation:
Department of Materials Science and Engineering, M.I.T., Cambridge, MA 02139
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Abstract

Microstructural evolution in thin-film strips is of interest due to the direct effect of grain structure on integrated circuit interconnect reliability and resistance to electromigration-induced failure. We have explored the evolution of interconnect grain structure via a two-dimensional grain growth simulation. We focus on the strip's transformation to the bamboo structure, in which individual grains traverse the width of the strip. We find that the approach to a fully bamboo structure is exponential, and that the rate of transformation is inversely proportional to the square of the strip width. When the simulation is extended to model grain boundary pinning due to grooving at grain boundary – free surface intersections, we find that there exists a maximum strip width to thickness ratio beyond which the transformation to the bamboo structure does not proceed to completion. By using our simulation results in conjunction with a “failure unit” model for electromigration-induced failure [4] we are able to reproduce the experimentally observed abrupt increase in time-to-failure below a critical strip width, and also model the reliability as a function of annealing conditions.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 225: Symposium G – Materials Reliability Issues in Microelectronics , 1991 , 219
Copyright
Copyright © Materials Research Society 1991

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References

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