Si/Ge heterostructures are one of the most promising performance boosters for next generation CMOS circuits. Lattice mismatch between Si and Ge enables us to manipulate lattice strain, that is, strain engineering is possible. The strain highly alters band structures and gives rise to band splitting and/or effective mass reduction, which brings significant mobility enhancement of the carriers in the strained channel.

High mobility channels such as strained-Si and strained-Ge can be formed on strain-relaxed SiGe buffer layers called SiGe virtual substrates (VS). Since the property of the SiGe VS directly affects that of the overgrown channel layer, creating high-quality SiGe VS is highly required to obtain high performance devices. One critical problem is a very large surface roughness arising on the SiGe VS. So-called crosshatch pattern appears on the surface, irrespective of growth methods. Since strain field coming from the underlying misfit dislocation arrays is responsible for this roughness formation, it is very difficult to create a roughness-free surface.

To overcome this problem, we employed chemical mechanical planarization (CMP) for the purpose of eliminating the roughness. Since CMP is established technology for Si wafer production, it is reasonably applicable to SiGe. Adopting the similar process as Si CMP, we demonstrated that an initial roughness of larger than 10 nm was reduced considerably down to less than 1 nm.

Post-CMP cleaning is an additional issue of great importance for regrowth of device channel structures. We found that the roughness increased during post-CMP cleaning process due to laterally nonuniform etching rate of the SiGe surface. To overcome this, we optimized the cleaning procedure, especially cleaning solution, and successfully obtained very smooth surface with RMS roughness of less than 0.4 nm, the lowest value ever obtained for SiGe surfaces.

The planarized SiGe VS was applied to strained channel structures. Strained Si modulation doped structure was fabricated on the planarized SiGe VS with a Ge concentration of 30 %. The electron Hall mobility obtained from the structure with CMP was 4 times higher than the reference structure without CMP, which is a clear evidence that the roughness-related carrier scattering can be well suppressed by the planarization. Strained Ge channel modulation doped structure was also fabricated on the SiGe VS with much higher Ge concentration (65 %). Although the roughness was much larger than 10 nm due to the high Ge concentration, the surface smoothness less than 1 nm was obtained by CMP. As a result, hole mobility enhancement factor over the reference sample without CMP was found to reach as high as 8 at low temperature and 1.8 at room temperature. These results clearly indicate that CMP is very promising technology for high performance strained Si/Ge based CMOS circuit.