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Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array beyond 90nm CMOS Technology

Published online by Cambridge University Press:  01 February 2011

Chungho Lee ,
Udayan Ganguly  and
Edwin C. Kan
Chungho Lee
Affiliation:
School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, U.S.A.
Udayan Ganguly
Affiliation:
School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, U.S.A.
Edwin C. Kan
Affiliation:
School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853, U.S.A.
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Abstract

Experimental characterization of nanocrystal formation in gate trenches were performed, which includes the analyses of number fluctuation, the size distribution, and the correlation of the size and number density in gate patterns with various feature sizes from 50nm to 150nm. The gate regions with 51nm oxide wall are defined by e-beam lithography and reactive ion etching (RIE). By using direct-deposit self-assembly (i.e., evaporation and post-annealing), Au, Ag, and Pt nanocrystals are formed on the gate tunneling oxide. From the statistical evaluation by scanning electron microscopy (SEM) observation, the number fluctuation of nanocrystals in a gate trench could be always controlled under 12%, while it follows the Poisson distribution in the unconstrained self-assembly. This is mainly due to the confinement effect by the trench sidewalls, corners, and edges. The current study demonstrated that the direct-deposit self-assembly process could be successfully adapted beyond 90nm metal nanocrystal memory technology with satisfactory parametric yield in the nanocrystal number density.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 830: Symposium D – Materials and Processes for Nonvolatile Memories , 2004 , D5.4
Copyright
Copyright © Materials Research Society 2005

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References

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