Hostname: page-component-586b7cd67f-r5fsc Total loading time: 0 Render date: 2024-11-25T18:40:31.225Z Has data issue: false hasContentIssue false

Channel Profile Engineering of MOSFETs using Delta Doping

Published online by Cambridge University Press:  22 February 2011

Andrew C. G. Wood
Affiliation:
University of Newcastle-upon-Tyne, Dept. of Electrical and Electronic Engineering, Merz Court, Newcastle-upon-Tyne, NEI 7RU, United Kingdom.
Anthony G. O'Neill
Affiliation:
University of Newcastle-upon-Tyne, Dept. of Electrical and Electronic Engineering, Merz Court, Newcastle-upon-Tyne, NEI 7RU, United Kingdom.
Get access

Abstract

The influence of the location, dose and width of the doping spike in a delta doped MOSFET is investigated theoretically. Calculations are performed for a range of n and p type 5M0SFETS, and the importance of each design parameter of the device is assessed. The optimum device has a delta layer around 2 0nm deep, with a sheet doping density around 1012cm−2 for the pMOSFET and 5.1011cm−2 for the nMOSFET. The effect of diffusion of the dopant during processing on the device performance is also considered, and it is found that this causes a shift in the threshold voltage of the device. The layer width should ideally be kept below 5nm.

Type
Research Article
Copyright
Copyright © Materials Research Society 1991

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Van Gorkum, A. A., Nakagawa, K. and Shiraki, Y., Jap. J. Appl. Phys. 26, L1933 (1987).CrossRefGoogle Scholar
2. Zeindl, H. P., Wegehaupt, T., Eisele, I., Oppolzer, H., Reisinger, H., Temple, G. and Koch, F., Appl. Phys. Lett. 50, 1164 (1987).CrossRefGoogle Scholar
3. Mattey, N. L., Hopkinson, M., Houghton, R. F., Dowsett, M. G., McPhail, D. S., Whall, D. S., Parker, E. H. C., Booker, G. R. and Whitehurst, J., Thin Solid Films 184, 15 (1990);CrossRefGoogle Scholar
Mattey, N. L., Dowsett, M. G., Parker, E. H. C., Whall, T. E., Taylor, S. and Zhang, J. F., Appl. Phys. Lett. 57, 1648 (1990).CrossRefGoogle Scholar
4. Zrenner, A., Reisinger, H., Koch, F. and Ploog, K., Proc. 17th Int. Conf. Phys. Semiconductors, San Fransisco, 1984, p325.Google Scholar
5. Schubert, E. F. and Ploog, K., Jap. J. Appl. Phys. 24. L608 (1985).CrossRefGoogle Scholar
6. Malik, R. J., Aucoin, T. R., Ross, R. L., Board, K., Wood, C. E. C. and Eastman, L. F., Electron. Lett. 16, 836 (1980).CrossRefGoogle Scholar
7. Schubert, E. F., Fischer, A. and Ploog, K., IEEE Trans. Electron Devices, ED33, 625 (1986).Google Scholar
8. Yamaguchi, K. and Shiraki, Y., IEEE Trans. Electron Devices, ED35, 1909 (1988).CrossRefGoogle Scholar
9. Nakagawa, K., Van Gorkum, A. A. and Shiraki, Y., Appl. Phys. Lett. 51, 1869 (1989).CrossRefGoogle Scholar
10. Board, K., Chandra, A., Wood, C. E. C., Judaprawira, S. and Eastman, L. F., IEEE Trans. Electron Devices, ED28 505 (1981).CrossRefGoogle Scholar
11. Yamaguchi, K., Shiraki, Y., Katayama, Y. and Murayama, Y., Jap. J. Appl. Phys. 22–1, 267 (1983).CrossRefGoogle Scholar
12. HFIELDS device model, University of Bologna, Italy.Google Scholar
13. Tam, S., ko, P -K and Hu, C., IEEE Trans. Electron Devices ED31, 1116 (1984).Google Scholar
14. Mattey, N. L. et al, to be published.Google Scholar