Hostname: page-component-586b7cd67f-l7hp2 Total loading time: 0 Render date: 2024-11-23T15:11:41.873Z Has data issue: false hasContentIssue false
  • English
  • Français

The Behavior of Ion Implanted Silicon During Ultra-High Temperature Annealing

Published online by Cambridge University Press:  01 February 2011

Amitabh Jain
Amitabh Jain*
Affiliation:
[email protected], Texas Instruments Inc., Silicon Technology Development, 13560 North Central Expressway, MS 3737, Dallas, Texas, 75243, United States
Get access

Abstract

Ultra-high temperature annealing is emerging as a promising technique for annealing ion implanted layers with a view to maximizing electrical activation while minimizing dopant diffusion. In order to ensure successful implementation, several materials-related problems have been under study. Since the time scale of the process is short, diffusion in the amorphous phase may dominate the final profile. In general, the residual disorder after anneal can be higher than with current anneal processes. However, the short time scale of the process curtails the opportunity for movement of dislocations into regions where the electrical behavior of a device would be affected. An additional effect of the limited time scale is the ability of silicon to plasto-elastically support the high strain-rates that may arise during the anneal.

Keywords

annealingion-implantationlaser
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 912: Symposium C – Doping Engineering for Device Fabrication , 2006 , 0912-C04-04
Copyright
Copyright © Materials Research Society 2006

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1 Mehrotra, M., Hu, J. C., Jain, A., Hattangady, S., Reddy, V., Aur, S. and Rodder, M., Proc. Intl. Electron Devices Meeting, 419 (1999).Google Scholar
2 Jain, Amitabh in Rapid Thermal and other Short-Time Processing Technologies, edited by Roozeboom, I F., Gelpey, J.C., Ozturk, M.C., Reid, K. and Kwong, D.L., 197th Electrochemical Society Meeting, 33 (2000).Google Scholar
3 Mayur, A.J., Jaggi, A., and Jain, A., 8th International Conference on Advanced Thermal Processing of Semiconductors – RTP 2000 edited by Lojek, B., 196 (2000).Google Scholar
4 Jain, S. C., Schoenmaker, W., Lindsay, R., Stolk, P. A., Decoutere, S., Willander, M., and Maes, H. E., J Appl. Phys. 91, 8919 (2002).Google Scholar
5 Jain, Amitabh, Mat. Res. Soc. Symp. Proc. vol. 810, C5.6.1 (2004).Google Scholar
6 Baumgart, H., Phillipp, F., Rozgonyi, G.A. and Gosele, U., Appl. Phys. Lett. 38, 95 (1981).Google Scholar
7 Patel, J.R. and Chauduri, A.R., J. Appl. Phys. 34, 2788 (1963).Google Scholar
8 Schroter, W., Brion, H.G. and Siethoff, H., J. Appl. Phys. 54, 1816 (1983).Google Scholar
9 Widmer, A.E. and Rehwald, W., J. Electrochem Soc. 133, 2403 (1986).Google Scholar
10 Hebb, Jeffrey P. and Jensen, Klavs F., IEEE Trans. Semicond. Manuf. 11, 99 (1998).Google Scholar
11 Gable, K. A., Robertson, L. S., Jain, Amitabh and Jones, K. S., J. Appl. Phys. 97, 044501 (2005).Google Scholar
12 Bu, Haowen and Jain, Amitabh, personal communication.Google Scholar