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Statistical Modeling of Grain-Enhanced Polysilicon Thin-Film Transistor in Consideration of Grain Boundary Distribution

Published online by Cambridge University Press:  21 March 2011

C. F. Cheng ,
M. C. Poon ,
C. W. Kok  and
M. Chan
C. F. Cheng*
Affiliation:
Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
M. C. Poon
Affiliation:
Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
C. W. Kok
Affiliation:
Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
M. Chan
Affiliation:
Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
*
*Correspondence to Tel: (852) 2358 7059, E-mail: [email protected]
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Abstract

A probabilistic model to predict the statistical distribution of grain boundaries in the thin-film transistor (TFT) with an arbitrary transistor-to-grain size ratio is proposed in this paper. Performance of the TFTs, such as carrier mobility, can be estimated and the corresponding performance variation of the fabricated devices becomes predictable when the statistical distribution of grain boundaries is known. The proposed model is still applicable even when the transistor size becomes comparable to the grain size. Reliability and accuracy of the modeling results have been extensively verified by experimental data. It is believed that the model can provide design and optimization guidelines of device variation for grain-enhanced polysilicon TFT technology.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 808: Symposium A – Amorphous and Nanocrystaline Silicon Science and Technology-2004 , 2004 , A4.13
Copyright
Copyright © Materials Research Society 2004

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References

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