Selective rapid thermal chemical vapor deposition (RTCVD) of TiSi2 is a promising alternative to the conventional self-aligned suicide (SALICIDE) process to form low-resistivity contacts to ultra-shallow source/drain junctions of deep submicron MOS transistors. The process makes use of TiCl4 and SiH4 as the Ti and Si source gases in a temperature range of 750 – 825 °C. The primary advantage of the process over the conventional SALICIDE process is that by providing sufficient levels of Si from the gas phase, junction consumption can be eliminated. Furthermore, the process eliminates wet etch and reduces the number of process steps from four to one. For the process to be compatible with CMOS manufacturing, low-resistivity TiSi2 deposition must be achieved on both source/drain junctions as well as the poly cry stalline silicon gate electrode. It is the objective of this paper to compare basic characteristics of the process on these two surfaces. The results indicate that the crystallinity of the surface on which TiSi2 is deposited can impact the nature of the deposited film. Our experimental results indicate enhanced Si consumption on polysilicon, smaller TiSi2 grains and consequently higher sheet resistance. However, the process conditions and TiSi2 thickness can be optimized to achieve consumption free TiSi2 deposition on the junctions with acceptable performance on polysilicon.