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Response Surface for CMOS Self-Aligned Titanium Silicide Process

Published online by Cambridge University Press:  22 February 2011

A. K. Nanda
Affiliation:
AT&T Bell Labs, Allentown, PA 18103
S. Meester
Affiliation:
AT&T Bell Labs, Holmdel, NJ 07733
C. W. Wilkins
Affiliation:
AT&T Bell Labs, Allentown, PA 18103
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Abstract

Sputtered deposited titanium films on silicon substrates were used to study the effects of first rapid thermal anneal temperature, duration of anneal time and thickness of the titanium films for TiSi2 formation. A central composite, coupled with a cross design was used to analyze response surface. Empirical models were developed and contour plots were generated to describe the outcome of the first anneal. A window of operation to control the process of titanium silicide formation was recommended. Response surface analysis of data revealed an operating window of ±10° C for RTA1 for stable TiSi2 formation. Within this window of operation, the within wafer uniformity was found to be at its minimum. Anneal time was found to have minimum effect on the variability although sheet resistance decreases monotonically with increasing anneal time. Thickness of titanium films were found to be very critical in determining final TiSi2 thickness as determined by RBS and/or XRF techniques.

Type
Research Article
Copyright
Copyright © Materials Research Society 1994

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References

REFERENCES

[1] Murarka, S. P., “Silicides for VLSI Applications,” Academic Press, 1983.Google Scholar
[2] DeLanerolle, N., Hoffman, D., and Ma, D., “Titanium Silicide Growth by Rapid Thermal Processing of Ti Films Deposited on Lightly Doped and Heavily Doped Silicon Substrates,” J. Vac. Sci. Technol., Vol. 5, pp. 16891695, 1987.CrossRefGoogle Scholar
[3] Lasky, Jerome B., Nakas, James S., Cain, Orison J., and Geiss, Peter, “Comparison of Transformation to Low Resistivity Phase and Agglomeration of TiSi2 and CoSi2 ,” IEEE Trans. Electron. Dev., Vol. 38, pp. 262268, 1991.CrossRefGoogle Scholar
[4] Ting, C. Y., d'Heurle, F. M., Iyer, S. S. and Fryer, P. M., “High Temperature Process Limitation on TiSi2 ,” J. Electrochem, Soc.: Vol. 133 (12), Dec. 1986, 26212625.CrossRefGoogle Scholar
[5] Montgomery, D. G., “Design and Analysis of Experiment,” 3rd ed., John Wiley, New York 1991.Google Scholar
[6] BBN Software Products Corporation, 10 Fawcett Street, Cambridge, MA.Google Scholar