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Optimization of Deposition Thickness and Over Polishing Time to Minimize Wafer Level Topography in Copper CMP

Published online by Cambridge University Press:  01 February 2011

J.M. Kang ,
Shaoyu Wu ,
T. Selvaraj ,
Benfu Lin  and
P.D. Foo
J.M. Kang
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore
Shaoyu Wu
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore
T. Selvaraj
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore
Benfu Lin
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore
P.D. Foo
Affiliation:
Institute of Microelectronics, 11 Science Park Road, Singapore
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Abstract

Topography after Cu CMP is one of the main issues in constructing reliable Cu interconnects. The wafer level topography is greatly influenced by many polishing properties such as removal non-uniformity and planarization efficiency, and also by many polishing variables. Among the variables, Cu deposition thickness and over polishing time are easily controllable, and closely related to the topography. For a given polishing condition, the topography can be minimized through the optimization of Cu deposition thickness and over polishing time. A model is proposed to account for the correlation between these variables and the wafer level topography. Numerical result of this model shows a strong dependency of optimized Cu deposition thickness and over polishing time on the removal non-uniformity, dishing susceptibility and over plated bump size.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 732: Symposium I – Chemical-Mechanical Planarization , 2002 , I4.13
Copyright
Copyright © Materials Research Society 2002

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References

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