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Optimisation and Simulation of an Alternative nano-flash Memory: the SASEM device.

Published online by Cambridge University Press:  01 February 2011

C. Krzeminski ,
E. Dubois ,
X. Tang ,
N. Reckinger ,
A. Crahay  and
V. Bayot
C. Krzeminski
Affiliation:
Institut Supérieur d'Electronique de Microélectronique et de Nanotechnologies, UMR CNRS 8520, Avenue Poincaré, Cité Scientifique, BP 69, 59652 Villeneuve d'Ascq, France.
E. Dubois
Affiliation:
Institut Supérieur d'Electronique de Microélectronique et de Nanotechnologies, UMR CNRS 8520, Avenue Poincaré, Cité Scientifique, BP 69, 59652 Villeneuve d'Ascq, France.
X. Tang
Affiliation:
Microelectronics Laboratory, Université Catholique de Louvain, Place du Levant, 1348 Louvain-La-Neuve, Belgium.
N. Reckinger
Affiliation:
Microelectronics Laboratory, Université Catholique de Louvain, Place du Levant, 1348 Louvain-La-Neuve, Belgium.
A. Crahay
Affiliation:
Microelectronics Laboratory, Université Catholique de Louvain, Place du Levant, 1348 Louvain-La-Neuve, Belgium.
V. Bayot
Affiliation:
Microelectronics Laboratory, Université Catholique de Louvain, Place du Levant, 1348 Louvain-La-Neuve, Belgium.
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Abstract

Process simulation are performed in order to simulate the full fabrication process of an alternative nano-flash memory in order to optimise it and to improve the understanding of the dot storage formation. The influence of various parameters (oxidation temperature, nanowire shape) have been investigated.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 830: Symposium D – Materials and Processes for Nonvolatile Memories , 2004 , D1.6
Copyright
Copyright © Materials Research Society 2005

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References

REFERENCES

[1] Tang, X. et al., Solid-State Electronics, 44, 2259 (2000)Google Scholar
[2] Tang, X., “Fabrication, characterization and simulation of SOI single-electron devices.”, Phd. Thesis, Université Catholique de Louvain, April 2001.Google Scholar
[3] Ho, C. P. and Plummer, J. D., J. Electrochem. Soc: solid state science and technology, Vol. 126, No. 9, 1516 (1979)Google Scholar
[4] Ho, C. P. and Plummer, J. D., J. Electrochem. Soc: solid state science and technology, Vol. 126, No. 9, 1523 (1979).Google Scholar
[5] Deal, B. E. and Grove, A. S., Journal of Applied Physics, Vol. 36, No. 12, 3770 (1965).Google Scholar
[6] Merz, W. and Strecker, N., Mathematical Methods in Applied Sciences, 1165 (1994).Google Scholar
[7] ISE DIOS, Process Simulator V6.0, ISE-TCAD.Google Scholar
[8] Senez, V., Collard, D., Baccus, B. and Lebailly, J., J. Appi. Phys., Vol. 43, no. 5, 720 (1996).Google Scholar