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Microbump Impact on Reliability and Performance in Through-Silicon Via Stacks

Published online by Cambridge University Press:  10 August 2011

Aditya P. Karmarkar  and
Xiaopeng Xu
Aditya P. Karmarkar
Affiliation:
Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh 500032, India.
Xiaopeng Xu
Affiliation:
Synopsys, Inc., Mountain View, CA 94043, U.S.A.
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Abstract

The impact of microbump geometry, layout and underfill material properties on the device performance as well as the structural reliability is examined. Numerical simulations reveal that the magnitude of n-type carrier mobility change correlates with the increase in the underfill CTE and modulus as well as microbump pitch and height, but the decrease in the microbump radius. The crack driving force dependence on material property and geometry differs from that of mobility change. While the driving force is crack location dependent, the greater crack driving force corresponds to larger underfill CTE and bump radius, but smaller underfill modulus and microbump pitch.

Keywords

thermal stressesmicroelectronicssimulation
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1335: Symposium O – Materials, Processes, and Reliability for Advanced Interconnects for Micro- and Nanoelectronics , 2011 , mrss11-1335-o08-05
Copyright
Copyright © Materials Research Society 2011

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References

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