Hostname: page-component-586b7cd67f-dsjbd Total loading time: 0 Render date: 2024-11-25T17:38:18.523Z Has data issue: false hasContentIssue false
  • English
  • Français

Material Properties of GaAs-on-Si and Fabrication of Digital Integrated Circuits

Published online by Cambridge University Press:  28 February 2011

N. Clhand ,
F. Ren ,
S. N. G. Chu ,
A. M. Sergent ,
T. Boone  and
D. V. Lang
N. Clhand
Affiliation:
At&t Bell Laboratories, Murray Hill, New Jersey 07974
F. Ren
Affiliation:
At&t Bell Laboratories, Murray Hill, New Jersey 07974
S. N. G. Chu
Affiliation:
At&t Bell Laboratories, Murray Hill, New Jersey 07974
A. M. Sergent
Affiliation:
At&t Bell Laboratories, Murray Hill, New Jersey 07974
T. Boone
Affiliation:
At&t Bell Laboratories, Murray Hill, New Jersey 07974
D. V. Lang
Affiliation:
At&t Bell Laboratories, Murray Hill, New Jersey 07974
Get access

Abstract

We have found that the surface morphology of GaAs grown on Si by MBE is smoother at lower growth temperatures (<500° C), but that the crystalline properties improve at higher growth temperatures (575-600°C). After thermal annealing at 850°C for 15 rai the TEM plan-views indicate that the dislocation density on the surface is reduced by a factor of 4 only. However, the TEM cross-sections indicate a much larger reduction of dislocations in highly dislocated regions near the GaAs/Si interface. Dislocations which are loops or tangles tend to shrink and clean up after annealing leaving a larger volume of GaAs free from, or with fewer, dislocations. The density of electron deep levels reduces with increasing thickness. Electron traps M1, M3 and M4 are not seen when a high purity As is used. For high device performance, the GaAs buffer layer thickness should be at least 2 µm. Although the wafer warpage increases from 7 µm to 52 µm as the GaAs thickness increases from 1.2 µm to 4.2 µm on 7.5 cm wafers, the wafers are as fiat as the original Si wafers under vacuum clamping. Wafer warpage reduced significantly when GaAs was grown selectively through a Si shadow mask. For 1 µm gate MESFET's, σvT was 65 mV on a 3.5 × 3 cm2 wafer area with gmax = 153 mS/ram. A minimum propagation delay of 52 ps/stage at a power dissipation of 1.3 mW/gate was measured for the 19 stage DCFL ring oscillators with 40= yield. Conductivity of the Si substrate and GaAs buffer layer posed no problem in channel isolation. The divide-by-two circuits performed the frequency dividing operation up to 1.8 GHz. The study shows that GaAs-on-Si has a great potential for digital IC's.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 116 , 1988 , 205
Copyright
Copyright © Materials Research Society 1988

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] Choi, H. K., Turner, G. W., and Tsaur, B-Y., Mat. Res. Soc. Symp. Proc. vol. 91, 213 (1987).Google Scholar
[2] See, for a review, Cho, A. Y., p. 91, Proceedings of the International Electron Device Meeting 1987, Washington, D.C. Google Scholar
[3] Shaw, D. W., Mat. Res. Soc. Symp. Proc. vol. 91, 15 (1987).CrossRefGoogle Scholar
[4] Shichijo, H., Tran, L. T., Matyi, R. J., and Lee, J. W., Mat. Res. Soc. Symp. Proc. vol. 91, 201 (1987).Google Scholar
[5] Fischer, R., Klein, J., Peng, C. K., Gedymin, J. S., and Morkoc, H., IEEE Electron Dev. Lett. EDL–7, 112 (1986).Google Scholar
[6] Tran, L. T., Matyi, R. J., Shichijo, H., Yuan, H. T. and Lee, J. W., IEEE Electron Dev. Lett. EDL–8, 50 (1987).Google Scholar
[7] Kroemer, H., Mat. Res. Soc. Symp. Proc. vol. 67, 3 (1986).Google Scholar
[8] Chand, N., Ziel, J. P. van der, Dupuis, R. D., Sergent, A. M., Optoelectronics-Device and Technologies 2, 329 (1987).Google Scholar
[9] Chand, N., People, R., Baiocchi, F. A., Wecht, K. W. and Cho, A. Y., Appl. Phys. Lett., 49, 815 (1986).Google Scholar
[10] Chand, N., Fischer, R., Sergent, A. M., Lang, D. V., Pearton, S. J. and Cho, A. Y., Appl. Phys. Lett. 51, 1013 (1987).Google Scholar
[11] Lee, J. W., Mat. Res. Soc. Symp. Proc. vol. 67, 29 (1986).Google Scholar
[12] Biegelsen, D. K., Ponce, F. A., Smith, A. J., and Tramontana, J. C., Mat. Res. Soc. Symp. Proc. vol. 67, 45 (1986).CrossRefGoogle Scholar
[13] Hull, R. and Fischer-Colbrie, A., Appl. Phys. Lett. 50, 851 (1987).Google Scholar
[14] Chand, N., Allam, J., Gibson, J. M., Capasso, F., Beltram, F., Macrander, A. T., Hutchinson, A. L., Hopkins, L. C., Bethea, C. G., Levine, B. F., and Cho, A. Y., J. Vac. Sci. Technol. B5, 822 (1987).Google Scholar
[15] Lang, D. V., Cho, A. Y., Gossard, A. C., Ilegems, M., and Wiegmann, W., J. Appl. Phys. 47, 2558 (1976).CrossRefGoogle Scholar
[16] Chand, N., Miller, R. C., Sergent, A. M., Sputz, S. K. and Lang, D. V., To be printed in Appl. Phys. Lett., May 1988.Google Scholar
[17] Lee, J. W., Shichijo, H., Tsai, H. L., and Matyi, R. J., Appl. Phys. Lett. 50, 31 (1987).Google Scholar
[18] Choi, C., Otsuka, N., Munns, G., Houdre, R., Morkoc, H., Zhang, S. L., Levi, D., and Klein, M. V., Appl. Phys. Lett. 50, 992 (1987).Google Scholar
[19] Chand, N., Ziel, J. P. van der, Weiner, J. S., Sergent, A. M. and Cho, A. Y., Appl. Phys. Lett., to be published.Google Scholar
[20] Nonaka, T., Akiyama, M., Kawarada, Y. and Kaminishi, K., Jpn. J. Appl. Phys. 23, L919 (1984).Google Scholar
[21] Ren, F., Chand, N., Garbinski, P., Wu, C. S., Urbanek, L. D., Fullowon, T. and Shah, N. J., IEEE Electron Device Lett., to be published.Google Scholar