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Long Time Data Retention and A Mechanism in Ferroelectric-Gate Field Effect Transistors with HfO2 Buffer Layer

Published online by Cambridge University Press:  01 February 2011

Koji Aizawa ,
Yoshihito Kawashima  and
Hiroshi Ishiwara
Koji Aizawa
Affiliation:
Precision & Intelligence Laboratory, Tokyo Institute of Technology, 4259-R2–19 Nagatsuta, Midori-ku, Yokohama 226–8503, Japan
Yoshihito Kawashima
Affiliation:
Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259-S2–9 Nagatsuta, Midori-ku, Yokohama 226–8503, Japan
Hiroshi Ishiwara
Affiliation:
Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, 4259-S2–9 Nagatsuta, Midori-ku, Yokohama 226–8503, Japan
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Abstract

A mechanism of the long-time data retention in the p-channel MFIS FETs with Pt/SBT/HfO2/Si gate structures was proposed. The MFIS FETs used in this study exhibited the drain current on/off ratio of approximately 6×103 even after 30 days had elapsed at room temperature. From the leakage current characteristics of the MFIS diode, the bulk leakage current density lower than 10-12 A/cm2 was presumed for 30-days data retention. On the other hand, we showed that the decrease of on-state drain current in the retention characteristics was explained by the flat-band voltage shift of approximately -0.3V for 30 days toward negative voltage direction. Therefore, it was also found that the trapped charge density as low as 1011 cm-2 was needed for obtaining the data retention of 30 days.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 830: Symposium D – Materials and Processes for Nonvolatile Memories , 2004 , D2.9
Copyright
Copyright © Materials Research Society 2005

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References

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