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Improved Al-Via Fill Process Technology for Sub-0.251µm Interconnect

Published online by Cambridge University Press:  10 February 2011

S. S. Sengupta ,
M. Narasimhan ,
S. Lee ,
M. Abburi  and
G. Yao
S. S. Sengupta
Affiliation:
VLSI Technology, Inc., 1109 McKay Drive, M/S 02, San Jose, CA 95131 [email protected]
M. Narasimhan
Affiliation:
Applied Materials, Inc., 3050 Bowers Avenue, Santa Clara, CA 95054.
S. Lee
Affiliation:
Applied Materials, Inc., 3050 Bowers Avenue, Santa Clara, CA 95054.
M. Abburi
Affiliation:
Applied Materials, Inc., 3050 Bowers Avenue, Santa Clara, CA 95054.
G. Yao
Affiliation:
Applied Materials, Inc., 3050 Bowers Avenue, Santa Clara, CA 95054.
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Abstract

In this paper, a simple and improved method for Al via fill is demonstrated. The ALPS (Aluminum Low Pressure Seed) technique was used to deposit a smooth, highly conformal Al seed layer over an all-IMP (ionized metal plasma) Ti/TiN/Ti stack. Subsequent warm Al deposition was carried out in a conventional warm Al chamber. The ALPS method was compared to standard hot Al deposition. Physical SEM characterization and electrical data showed lower via resistances, with better yield for ALPS. No voiding was observed even within unlanded vias. With the ALPS seed layer, the IMP Ti/TiN/Ti liner stack provided a superior wetting surface compared to an IMP Ti-only liner which resulted in voids within unlanded vias. Electrical data obtained for ALPS- and hot Al-deposited Kelvin vias and via chains with various via/metal underlaps were compared with conventional CVD W plugs (using IMP TiN as the glue layer). Both Al fill methods gave lower via resistance compared with W plugs, as expected.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 564: Symposium N – Advanced Interconnects and Contacts , 1999 , 437
Copyright
Copyright © Materials Research Society 1999

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References

1. Atakov, E., Sriram, T.S., Dunnel, D., Pizzanello, S., Ohsaki, A., and Maekawa, K., Fourteenth VLSI Multilevel Metallization Conference (VMIC), 473 (1997).Google Scholar
2. Dixit, G.A., Chisholm, M.F., Jain, M.K., Weaver, T., Ting, L.M., Poarch, S., Mizobuchi, K., and Havemann, R.H., Proc. IEEE-IEDM, 105 (1994).Google Scholar
3. Singer, P., Semiconductor International 19(2), 89 (1996).Google Scholar
4. Barth, H.J., Mater. Res. Soc. Symp. 427, 253 (1996).10.1557/PROC-427-253Google Scholar
5. Rossnagel, S.M., J. Vac. Sci. Technol. B16 2585 (1998).10.1116/1.590242Google Scholar
6. Lau, G., Shan, E., Geha, S., Su, J., Wu, Z., Ponnekanti, S., and Yao, G., Fifteenth VLSI Multilevel Metallization Conference (VMIC), 180 (1998).Google Scholar
7. Sengupta, S.S. and Bothra, S., Proc. SPIE 3508, 110 (1998).10.1117/12.324042Google Scholar
8. Ito, N., Yamada, Y., Kikuta, K., and Kikkawa, T., Electronics and Communications in Japan, Part II: Electronics 79, 109 (1996).10.1002/ecjb.4420790211Google Scholar