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Electrical Properties of Stacked RTO/RTCVD Oxides as Gate Dielectrics

Published online by Cambridge University Press:  22 February 2011

V. Misra ,
X-L. Xu  and
J.J. Wortman
V. Misra
Affiliation:
North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, N.C. 27695-7911
X-L. Xu
Affiliation:
North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, N.C. 27695-7911
J.J. Wortman
Affiliation:
North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, N.C. 27695-7911
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Abstract

To meet the stringent demands of high quality gate performance in advanced devices, a more robust gate dielectric is needed. A stacked structure consisting of thermal oxide and deposited oxide is a potential candidate since it offers certain advantages over single layer oxides such as 1) reduced defect density, 2) reduced stress at the SiO2/Si interface due to stress compensation between the thermal and the deposited oxide, 3) less silicon consumption and 4) reduced thermal budget. In this study, stacked oxides consisting of RTO and RTCVD oxides are characterized. In contrast to other studies which use conventional LPCVD methods to form the top oxide, these stacked oxides have the advantages of rapid thermal and in-situ processing, which produces excellent bulk and interfacial properties. Electrical characterization has shown that these stacked oxides have superior performance compared to single layer furnace or deposited oxides.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 342: Symposium G – Rapid Thermal and Integrated Processing III , 1994 , 187
Copyright
Copyright © Materials Research Society 1994

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References

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