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Effect of Gate Dielectric on Performance of Polysilicon thin Film Transistors

Published online by Cambridge University Press:  21 February 2011

Miltiadis K. Hatalis ,
Ji-Ho Kung ,
Jerzy Kanicki  and
Arthur A. Bright
Miltiadis K. Hatalis
Affiliation:
Lehigh University, Dept. of Computer Science and Electrical Engineering, Bethlehem, PA 18015
Ji-Ho Kung
Affiliation:
Lehigh University, Dept. of Computer Science and Electrical Engineering, Bethlehem, PA 18015
Jerzy Kanicki
Affiliation:
IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY.
Arthur A. Bright
Affiliation:
IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY.
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Abstract

The effect of gate dielectric on the electrical characteristics of n-channel polysilicon thin film transistors was investigated. The following insulators were studied: silicon dioxide grown by wet oxidation, silicon dioxide deposited by plasma enhanced chemical vapor deposition (PECVD) and nitrogen-rich silicon nitride deposited by PECVD. It was observed that the effective electron mobility in TFTs having a deposited dielectric, either silicon nitride or silicon dioxide was higher than that measured in devices with grown silicon dioxide. The TFT leakage current was found to be lowest in devices with PECVD silicon nitride. Devices with deposited dielectrics did not degrade after a positive gate bias stress. However, reduction of the threshold voltage was observed in devices with PECVD silicon nitride, when they were subjected to a negative gate bias stress.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 182: Symposium C – Polysilicon Thin Films and Interfaces , 1990 , 357
Copyright
Copyright © Materials Research Society 1990

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