Hostname: page-component-586b7cd67f-vdxz6 Total loading time: 0 Render date: 2024-11-25T17:35:19.188Z Has data issue: false hasContentIssue false
  • English
  • Français

Current Issues and Future Trends in CMP Consumables for Oxide and Metal Polish

Published online by Cambridge University Press:  15 February 2011

M. Moinpour  and
A. Philipossian
M. Moinpour
Affiliation:
Intel Corporation, Santa Clara, CA 95052 USA
A. Philipossian
Affiliation:
Intel Corporation, Santa Clara, CA 95052 USA
Get access

Introduction

The recent advent of Chemical Mechanical Planarization (CMP) as a major process technology has had a significant impact on the semiconductor industry. Oxide CMP is a technology enabler for logic and DRAM devices with feature sizes less than (or equal to) 0.75 micrometer [1]. Similarly, tungsten CMP has become a technology enabler for 0.35 micron devices [2,3], and current trends indicate that it will continue to play a major role in future generations of IC technologies [4,5]. CMP can also provide a technological advantage in front-end process modules such as Shallow Trench Isolation [6].

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 427: Symposium K – Advanced Metallization for Future ULSI , 1996 , 243
Copyright
Copyright © Materials Research Society 1996

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] Renteln, P., Thomas, M. and Pierce, J., VMIV Proc., p. 57,1991.Google Scholar
[2] Rutten, M., Huynh, C., SRC Topical Conf. in CMP, July 1995.Google Scholar
[3] Kaufman, F., et. al., ”Chemical-Mechanical Polishing for Fabricating Patterned WMetal Features as Chip Interconnects”, J. Electrochem. Soc., Vol.138, No. 11., p. 3460, Nov., 1991.Google Scholar
[4] Sivaram, S., Bath, H., Leggett, R., Maury, A., Monnig, K., and Tolles, R., Solid State Tech., p. 87, 1992.Google Scholar
[5] Furumura, Y., et. al., ”CMP Roadmap for a Large Diameter Wafer”, Proceedings 24th Symposium on ULSl Ultra Clean Technology, Tokyo, p191, March 1995.Google Scholar
[6] Davari, B., Koburger, C., Schutz, R. et al., IEDM Tech. Digest, p. 61, 1989.Google Scholar
[7] Patrick, W. et. al., ”Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections” J. Electrochem. Soc., Vol.138, p. 1778, 1991.Google Scholar
[8] Cook, L., Wang, J., James, D. and Sethuraman, A., Semiconductor International,p. 141, Nov. 1995.Google Scholar
[9] Scherber, D. and Neville, M., Proceedings of the Symposium on Planarization Technology: CMP, Semicon West, 1994.Google Scholar
[10] Jairath, R., et. al., ”Chemical and Mechanical polishing: ProcessManufacturability”, Solid State Technology, p. 71, July 1994.Google Scholar
[11] Steigerwald, J., et al, J. Electrochem. Soc., 1995.Google Scholar
[12] German, R. Powder Metallurgy Science , (Princeton: Metal Powder Industry, 1984) pp. 9–54.Google Scholar
[13] Shaw, A., “Selection of Particle Sizing Technology for CMP slurries,” Abstract: Spring Meeting Materials Research Society, p. 203, 1995.Google Scholar
[14] Hayashi, Y., Proceedings 24th Symposium on ULSI Ultra Clean Technology, Tokyo, p. 182, March 1995.Google Scholar
[15] Tomozawa, M. et. al. “Effect of Pad Characteristics on Oxide Polishing Performance,” SRC Topical Conf. in CMP, July 1995.Google Scholar
[16] Jeong, H., Karaki-Doy, T. et. al., “New polishing by mechanical and chemical polishing techniques insensitive to pattern-topography for VLSI wafer,” Proceedings of MicroProcess, p. 121,1994.Google Scholar