Hostname: page-component-78c5997874-s2hrs Total loading time: 0 Render date: 2024-11-19T03:12:31.108Z Has data issue: false hasContentIssue false
  • English
  • Français

A Complete Stochastic Wiring Distribution for Gigascale Integration (GSI)

Published online by Cambridge University Press:  15 February 2011

Jeffrey A. Davis ,
John C. Eble ,
Vivek K. De  and
James D. Meindl
Jeffrey A. Davis
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, [email protected]
John C. Eble
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, [email protected]
Vivek K. De
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, [email protected]
James D. Meindl
Affiliation:
Microelectronics Research Center, School of ECE, Georgia Institute of Technology, 791 Atlantic Ave. Atlanta, GA 30332-0269, [email protected]
Get access

Abstract

Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. The distribution is then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum chip size for a ULSI system. In addition, this new distribution has been incorporated into a Generic System Simulator (GENESYS), that projects overall performance of future ULSI systems. Assuming various interconnect materials such as copper, aluminum, silicon dioxide, and low dielectric polymers, GENESYS has been used to examine the effects that each material has on overall performance of ASIC's over the next 15 years.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 427: Symposium K – Advanced Metallization for Future ULSI , 1996 , 23
Copyright
Copyright © Materials Research Society 1996

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

[1] Keys, R. W.., IEEEJournal of Solid-State Circuits, SC-17 (6), 1232–1233, (1982).Google Scholar
[2] Bakoglu, H. B., Circuits, Interconnections, and Packaging for VLSI, (Addison-Wesley Company, Reading, Mass., 1990).Google Scholar
[3] Sai-Halaz, G. A., Proceedings of the IEEE, 83 (1), 20–36 (1995).Google Scholar
[4] Donath, W. E., , W. E., IBM Journal of Research & Development, 2 (3), 152–155 (1981).Google Scholar
[5] Brews, J. R., Submicron Integrated Circuits, (Wiley, New York, 1989).Google Scholar
[6] Christie, P., Proceeding of the IEEE, 81 (10), 1492–1499, (1993).Google Scholar
[7] Donath, W. E., IEEE Transactions on Circuits and Systems, CAS-26 (4), 272–277 (1979).Google Scholar
[8] Landman, B. S. and Russo, R. L., IEEE Transaction on Computers, C–20, 1469–1479 (1971).Google Scholar
[9] Sakurai, T., IEEE Transactions on Electron Devices, 40, (1), 118–124 (1993).Google Scholar
[10]Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, 12–16, (1994).Google Scholar
[11] Masaki, A., Proceedings of the IEEE, 81, 1311–1324 (1993).Google Scholar