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Comparative Studies of Furnace and Rapid Thermal Passivation for Accumulation and Inversion Mode Polysilicon-On-Oxide Mosfets.

Published online by Cambridge University Press:  21 February 2011

S. Batra ,
K. Park ,
S. Banerjee  and
R. Sundaresan
S. Batra
Affiliation:
The University of Texas at Austin, Austin, TX - 78712
K. Park
Affiliation:
The University of Texas at Austin, Austin, TX - 78712
S. Banerjee
Affiliation:
The University of Texas at Austin, Austin, TX - 78712
R. Sundaresan
Affiliation:
Texas Instruments Inc., Dallas, TX - 75265
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Abstract

Carrier transport in the channel region of polysilicon thin film MOSFETs is affected by the presence of grain boundary potential barriers and is further complicated by the modulation of the grain boundary barrier height with gate voltage. Passivation of the trap sites with atomic hydrogen reduces the barrier height and thereby improves the performance of polysilicon transistors. In this paper, we demonstrate the effectiveness of Rapid Thermal Annealing (RTA) using Si3N4 as a solid source of H as a passivation technique for both inversion and accumulation mode polysilicon MOSFETs. ON/OFF ratios of 107 can be obtained by RTA passivation for inversion mode polysilicon MOSFETs compared to 106 after furnace passivation permitting the potential application of these MOSFETs both as load transistors in SRAMs as well as pass transistors in DRAMs. In contrast, the ON&OFF ratio of accumulation mode polysilicon MOSFETs does not show any improvement even though ID and VT improve with passivation. This is because of excessive back channel leakage in accumulation mode MOSFETs which increases with passivation.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 182: Symposium C – Polysilicon Thin Films and Interfaces , 1990 , 393
Copyright
Copyright © Materials Research Society 1990

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References

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