Published online by Cambridge University Press: 31 January 2011
With the increase in integrated circuit (IC) feature density, the quality of chemical mechanical polishing (CMP) becomes more important as the copper interconnects decrease in size. The optimization of the IC manufacturing process will be greatly enhanced if the nanoscale effects on CMP are better understood. CMP-related wear at the sub-micron scale, where a single particle affects the microstructure of individual copper features within the substrate, needs to be investigated to account for wafer-scale variations. Hardness is known to affect the material removal rate, but the grain level mechanism of the removal process is not yet well known. In this work, the orientation-dependence of wear has been investigated by performing nanoscale scratch tests on single crystal copper along different crystallographic planes, indentified using orientation imaging microscopy (OIM). An analysis of the surface forces and post-scratch topography produced during the scratch tests was conducted and the results have been interpreted from a CMP perspective. Ultimately, these results are expected to refine existing material removal rate models which do not consider the sensitivity of microstructure on the CMP process.