As the CMOS device dimensions continue to shrink, it is more and more critical to control the process parameters during mass production of advanced VLSI chips in order to achieve high yield and profitability. 2D dopant characterization is one of the critical techniques to resolve manufacturing excursions. A quick access to dopant distribution, especially precise delineation of p-n junction would readily provide critical information for many manufacturing issues, as well as device design and process development. Here we present our approaches to some of those issues with available techniques. The main techniques we used are dopant selective etching (DSE) and scanning probe microscopy based electrical measurements including scanning capacitance microscopy (SCM) and scanning spread resistance microscopy (SSRM). These techniques provided complementary results and showed strengths in solving different issues. We have successfully delineated junction of CMOS devices with 0.13 μm technology with source/drain extensions. Other applications, including diode leakage, well-well isolation, and buried layer delineation with the combination of these methods are presented.