As advanced CMOS scaling with FinFETs continues beyond the 10/7nm nodes, contact resistance (Rc) remains a dominant component affecting device performance. The FinFET Source/Drain (S/D) contact area has become smaller with fin pitch scaling, resulting in drastically increased Rc. To achieve higher drive currents and fully realize the performance gain from FinFET architectural changes, it is critical to continue to reduce contact resistivity (ρc) < 1.0x10-9 Ω.cm2 for both NMOS and PMOS. In this paper, we review the recent trends for ρc reduction for advanced CMOS devices and discuss approaches that have demonstrated reduction in ρc, such as in-situ heavily doped epitaxial films for S/D, advanced ion implantation and laser anneals. The implant techniques include pre-amorphization implants (PAI), dopant boosting implants, cryogenic (-100°C) implants for damage engineering and plasma doping (PLAD) for conformal doping of high aspect ratio (HAR) contacts. With such high levels of doping from epi and implants, advanced laser anneals are key for epitaxial regrowth and formation of metastable alloys for dopant supersaturation or segregation in top layers. Millisecond laser anneal (MSA) improves dopant activation and nanosecond laser anneal (NLA) permits superactivation, and both have become key enablers for ρc reduction. This paper also reviews two alternative contact approaches: dual silicide scheme and wrap-around contact (WAC), as potential pathways to further reduce Rc for advanced CMOS nodes.

This paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

Substantial increase of output current, and Ion / Ioff ratio for sub-7nm low power CMOS transistors, can be accomplished using a novel optoelectronic technology, which is 100% compatible with existing CMOS process flow. For RF or mixed signal ASICs, adding photonic components may improve the cut-off frequency, and reduce series resistance. Products that utilize power regulating devices, such as power MOSFETs, will benefit from the optoelectronic configuration to achieve much lower Rdson and high voltage at the same time. For semiconductor memories, such as DRAM or FLASH, the photonic technique may reduce the ERASE / WRITE / access time and improve the reliability.

Frequent switching of resistive memory cell may lead to a local accumulation of Joules heat in the device. Since the ReRAM cells are arranged in crossbar arrays with the two electrodes running perpendicular to each other, the heat generated in one device spreads via common electrode metal lines to the neighboring cells causing their performance degradation. Also cells that do not share any of the two electrodes (e.g. the diagonal array cells) with the hot device may also degrade provided the intermediate cells are set to an on-state establishing thus a continuous thermal conduction path between the heated and the probed device. It is found that the heat conduction along the active Cu electrode is more pronounced than that along the inert Pt electrode. Devices with Rh inert electrode performed better than those with Pt electrode due to better heat conductivity properties of Rh vs Pt. The heat dissipation is also found worse for a heated device with narrow and thin lines causing, however less degradation of more distant neighbor cells than for wide and thick metal lines. Finally, there is a trade-off between dissipating the heat quickly form the heated device to increase its maximum switching cycles and the heat exposure of the neighboring devices.

Impacts of a forming process on bipolar resistive switching (RS) characteristics in Pt/TaOx/Ta2O5/Pt cells were investigated. We found that the forming resulted in a transition from an initial state to a particular high resistance state (HRS) in most of the Pt/TaOx/Ta2O5/Pt cells. Evaluation of electrical characteristics after the transition to the particular HRS revealed that two modes of bipolar RS with the conventional polarity based on valence change mechanism and with the opposite polarity could be selectively obtained by adjusting the magnitude of the applied voltage. Moreover, the cell resistance decreased gradually during set processes in the bipolar RS with the opposite polarity.

Scanning tunneling microscopy and spectroscopy (STM/STS) are used to electronically switch atomically-thin memristors, referred to as “atomristors”, based on a graphene/molybdenum disulfide (MoS2)/Au heterostructure. A gold-assisted exfoliation method was used to produce near-millimeter (mm) scale MoS2 on Au thin-film substrates, followed by transfer of a separately exfoliated graphene top layer. Our results reveal that it is possible to switch the conductivity of a graphene/MoS2/Au memristor stack using an STM tip. These results provide a path to further studies of atomically-thin memristors fabricated from heterostructures of two-dimensional materials such as graphene and transition metal dichalcogenides (TMDs).

Using ab initio simulation, we study a ferroelectric layer of a few nanometers made of hafnia (HfO2) under the influence of Si doping with TiN electrodes. We evaluate the orthorhombic phase of Pca21 symmetry, its ferroelectric switching and the incidence of doping with silicon. We show that the ferroelectric switching can involve a 90° characteristic angle with corresponding activation energy which is lowered by a factor three due to Si doping at 3% at. A full MFM (Metal-Ferroelectric-Metal) model is derived in order to simulate finite-size effects. This model is compatible with a reversal of a polar HfO2:Si with a (111) preferential orientation. Validity and usefulness of such a model are discussed for ferroelectric devices optimization.