Article contents
Charge Trapping Analysis of High Speed Diamond FETs
Published online by Cambridge University Press: 06 February 2017
Abstract
Charge carrier trapping in diamond surface conduction field effect transistors (FETs) has been analyzed. For these devices two methods were used to obtain a negative electron affinity diamond surface; either plasma hydrogenation or annealing in an H2 environment. In both cases the Al2O3 gate dielectric can trap both electrons and holes in deep energy levels with emission timescales of seconds, while the diamond – Al2O3 interface traps exhibit much shorter time scales in the microsecond range. Capacitance-Voltage (CV) analysis indicates that these interface traps exhibit acceptor-like characteristics. Correlation with CV based free hole density measurements indicates that the conductance based interface trap analysis provides a method to quantify surface characteristics that lead to surface conduction in hydrogenated diamond where atmospheric adsorbates provide the acceptor states for transfer doping of the surface.
Keywords
- Type
- Articles
- Information
- Creative Commons
- This is an Open Access article, distributed under the terms of the Creative Commons Attribution licence (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted re-use, distribution, and reproduction in any medium, provided the original work is properly cited.
- Copyright
- Copyright © Materials Research Society 2017
References
REFERENCES
- 8
- Cited by