Hostname: page-component-78c5997874-mlc7c Total loading time: 0 Render date: 2024-11-09T07:28:35.408Z Has data issue: false hasContentIssue false
  • English
  • Français

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

Published online by Cambridge University Press:  09 March 2012

Behnam Sedighi ,
Mahdi Khafaji  and
Johann Christoph Scheytt
Behnam Sedighi*
Affiliation:
National ICT Australia (NICTA), Department of Electrical and Electronic Engineering, University of Melbourne, VIC 3010, Australia.
Mahdi Khafaji
Affiliation:
IHP, Frankfurt (Oder) 15236, Germany.
Johann Christoph Scheytt
Affiliation:
IHP, Frankfurt (Oder) 15236, Germany.
*
Corresponding author: B. Sedighi[email protected]
Get access Rights & Permissions [Opens in a new window]

Abstract

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

Keywords

Circuit Design and ApplicationsModellingSimulation and characterizations of devices and circuits
Type
Research Papers
Information
International Journal of Microwave and Wireless Technologies , Volume 4 , Special Issue 3: European Microwave Week 2011 , June 2012 , pp. 275 - 282
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2012

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

[1]Niknejad, A.M.: Siliconization of 60 GHz. IEEE Microw. Mag., 1 (2010), 78–85.CrossRefGoogle Scholar
[2]Takahashi, H.; Kosugi, T.; Hirata, A.; Murata, K.; Kukutsu, N.: 10-Gbit/s BPSK modulator and demodulator for a 120-GHz-band wireless link. IEEE Trans. Microw. Theory Tech., 5 (2011), 1361–1368.CrossRefGoogle Scholar
[3]Lu, L.; Zhang, X.; Funada, R.; Sum, C.S.; Harada, H.: Selection of modulation and coding schemes of single carrier PHY for 802.11ad multi-gigabit mmWave WLAN systems, in IEEE Symp. Computers and Communications (ISCC), Kerkyra, 2011, 348–352.Google Scholar
[4]Barale, F.; Iyer, G.B.; Perumana, B.G.; Sen, P.; Sarkar, S.; Rachamadugu, A.; et al. : Pulse Shaping and Clock Data Recovery for Multi-Gigabit Standard Compliant 60 GHz Digital Radio, in IEEE MTT-S Int. Microwave Symp. (IMS), Anaheim, 2010, 908–911.Google Scholar
[5]Khafaji, M.; Gustat, H.; Sedighi, B.; Ellinger, F.; Scheytt, J.C.: A 6-bit fully binary digital-to-analog converter in 0.25-µm SiGe BiCMOS for optical communications. IEEE Trans. Microw. Theory Tech., 9 (2011), 2254–2264.CrossRefGoogle Scholar
[6]Greshishchev, Y.M.; Pollex, D.; Wang, S.C.; Besson, M.; Flemeke, P.; Szilagyi, S.; et al. : A 56GS/S 6b DAC in 65 nm CMOS with 256 × 6b memory, in IEEE Int. Solid-State Cir. Conf. (ISSCC), San Francisco, 2011, 194–195.Google Scholar
[7]Nagatani, M.; Nosaka, H.; Yamanaka, S.; Sano, K.; Murata, K.: Ultrahigh-speed low-power DACs using InP HBTs for beyond 100-Gb/s/ch optical transmission systems. IEEE J. Solid-State Cirtcuits, 10 (2011), 2215–2225.CrossRefGoogle Scholar
[8]Kim, B.C.; Cho, M.; Kim, Y.; Kwon, J.: A 1 V 6-bit 2.4 GS/s Nyquist CMOS DAC for UWB systems, in IEEE MTT-S Int. Microwave Symp. (IMS), Anaheim, 2010, 912–915.Google Scholar
[9]Wu, X.; Palmers, P.; Steyaert, M.: A 130 nm CMOS 6-bit full Nyquist 3GS/s DAC. IEEE J. Solid-State Circuits, 11 (2008), 2396–2403.CrossRefGoogle Scholar
[10]Tseng, W.-H.; Wu, J.-T.; Chu, Y.C.: A CMOS 8-Bit 1.6-GS/s DAC with digital random return-to-zero. IEEE Trans. Circuits Syst. II Express Briefs, 1 (2011), 1–5.Google Scholar
[11]Savoj, J.; Abbasfar, A.; Amirkhany, A.; Jeeradit, M.; Garlepp, B.W.: A 12-GS/s phase-calibrated CMOS digital-to-analog converter for backplane communications. IEEE J. Solid-State Cirtcuits, 5 (2008), 1207–1216.CrossRefGoogle Scholar
[12]van den Bosch, A.; Borremans, M.A.F.; Steyaert, M.S.J.; Sansen, W.: A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter. IEEE J. Solid-State Circuits, 3 (2001), 315–324.CrossRefGoogle Scholar
[13]Cao, J.Lin, H.; Xiang, Y.; Kao, C.; Dyer, K.: A 10-bit 1GSample/s DAC in 90 nm CMOS for embeded applications, in IEEE Custom Integrated Circuits Conf. (CICC), San Jose, 2006, 166–169.Google Scholar
[14]Lin, C.-H.; van der Goes, F.; Westra, J.; Mulder, J.; Lin, Y.; Arslan, E.; et al. : A 12b 2.9 GS/s DAC with IM3 <− 60 dB beyond 1 GHz in 65 nm CMOS, in IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, 2009, 74–75.Google Scholar
[15]Razavi, B.: Principles of Data Conversion System Design, IEEE-Press, Piscataway, NJ, 1994.CrossRefGoogle Scholar
[16]Gray, P.R.; Hurst, P.J.; Lewis, S.H.; Meyer, R.G.: Analysis and Design of Analog Integrated Circuits, 4th ed., John Wiley, New York, 2001.Google Scholar
[17]Chen, T.; Gielen, G.: The analysis and improvement of a current steering DAC's dynamic SFDR-I: the cell dependent delay difference. IEEE Tran. Circuits Syst.-I, 1 (2006), 3–15.CrossRefGoogle Scholar
[18]Van den Bosch, A.; Steyaert, M.; Sansen, W.: SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters, in Int. Conf. Electronics Circuits and Systems (ICECS), Pafos, Cyprus, 1999, 1193–1196.Google Scholar