This chapter provides an introduction to ship structures and includes descriptions of structural arrangements of the most important types of merchant ships and the properties of the materials used. This is followed by a discussion of the need to consider ship structures at different levels of analysis (top-down approach). The role of structural modelling, and in particular modelling applicable to global strength, is described. In the second part of the chapter an overview of current practice in ship structural design is presented, in which similarities between merchant and warship structural design are highlighted. The role of classification societies is described as well as that of the IMO Goal-Based-Standards. A comparison of classification society rules follows. The role of computer-based techniques is discussed. In the last section recommendations for good practice in ship structural design are provided.

So far, we have been using (wasting?) one FPGA logic cell flip-flop to create each bit of RAM memory and one or more logic cells for each ROM bit. This is inefficient and, for anything more than a small memory array, could leave us without enough logic cells to implement the rest of our design or require a larger, more expensive device.

The optimum structural design of the hull girder is discussed in this chapter. In the first part, early efforts at optimisation are described: structural optimisation, topology and scantlings optimisation and nonlinear programming. The use of linear and sequential linear programming and its use in the MAESTRO program are described. The need to consider wider issues is discussed and the various single-parameter optimisation criteria described (design for X). Multi-objective optimisation criteria and Pareto optimality are discussed. The background to genetic algorithms and the fundamental theorem of genetic algorithms are presented. Single and multi-objective optimisation using genetic algorithms is described and illustrated with application to a catamaran structure. The analytic hierarchy process used in the ranking of different criteria put forward by stakeholders in an optimum structural design problem is described. This is applied in a case study described in the last part of the chapter that concerns the optimum structural design of a RoPax carrier. In this finite element models are used in the concept design stage to select a topology of the structure as well as the preliminary design stage. A series of criteria selected by a number of stakeholders are used as a basis for the optimisation process.

Available at https://LAoE.link/LAoE_Chapter_28O.pdf.

After configuring your breadboard for digital circuits, this lab invites you to look at integrated circuit logic gates; first examining their characteristics and foibles, then using them to carry out some Boolean logic operations.

Suppose you are faced with a signal that looks like that in : a signal of moderate frequency, polluted with some fuzz.

What problem do we meet today? We try to design a circuit that provides an output supply voltage that is constant despite fluctuations that may arise in both input voltage and output current loading.

This decoupling does not affect the behavior of the circuit, since the noise was harmless – but it does make the waveform prettier. (And we hope you are getting into the habit of always bypassing your power supplies in any case.)

This chapter reviews the a large family of relatively cheap primal heuristics that generally try to convert infeasible solutions obtained by solving the continuous relaxation of a MIP into feasible solutions. The review is conducted by following three main concepts, namely that of rounding a fractional point to an integer one, that of propagating the logical implication of a decision on a variable to other variables, and that of diving, i.e., sequentially make decisions on variables. The combinations of these concepts are extensively analyzed.

In this chapter we meet circuits that remember states of binary signals. Such circuits can be more versatile than the merely combinational circuits that we met earlier. Computers and most of the other digital devices we rely on would not be possible without a way to remember past events.

We aim to apply MOSFETs to form gates capable of Boolean logic and to look at some such binary operations.