Book contents
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
7 - Abutment System Configuration
Published online by Cambridge University Press: 05 May 2010
- Frontmatter
- Abstract
- Preface
- Contents
- List of Figures
- List of Plates
- List of Tables
- List of Algorithms
- Glossary of Terms
- 1 Introduction
- 2 Two-Dimensional Chip Design
- 3 Three-Dimensional Chip Technology
- 4 Three-Dimensional Circuit Topology
- 5 Three-Dimensional Cell Tessellation
- 6 Three-Dimensional Abutment System
- 7 Abutment System Configuration
- 8 Abutment System Evaluation
- 9 Conclusions
- A Layout Editor Configuration
- B Layout System Data Structures
- C Cell Description Rules
- D Circuits
- References
- Index
Summary
Overview
Aims
This chapter describes a set of preliminary layout experiments using the system of three-dimensional abutment just described. The experiments are designed to configure the system and prepare the way for the experiments described in the next chapter. Specifically, the following questions are addressed:
What are the important components of the merit functions?
How should the components of the merit functions be weighted?
What are the best algorithm control strategies?
Is the system behaving sensibly?
The system is deliberately designed to operate in a highly flexible manner, and a primary goal of this first set of experiments is to determine those settings of the system parameters which produce the best layouts according to metrics which are discussed. This involves the postulation and evaluation of merit function components to control both placement and routing. In addition, the effect of different algorithm control strategies on layout is investigated, particularly the effect of the cluster shape and routing space controls. Finally, the system is used on circuits which are known to have optimal embeddings in the three-dimensional framework, and the results are used to indicate that the system exhibits appropriate behaviour and that the chosen system parameters are suitable.
Methods
The general experimental method used to determine the effect of some parameter or algorithm control is now described. First, a set of circuits for which layouts are constructed is defined. A variety of mainly random logic circuits is chosen in order to measure the layout system behaviour for a range of circuits. Each circuit is described in terms of simple NAND gates.
- Type
- Chapter
- Information
- Three-Dimensional Integrated Circuit Layout , pp. 123 - 144Publisher: Cambridge University PressPrint publication year: 1991