Crossref Citations
This Book has been
cited by the following publications. This list is generated based on data provided by Crossref.
Barrera, T.
Griffith, J.
Robins, G.
and
Tongtong Zhang
1993.
Closing the gap: Near-optimal Steiner trees in polynomial time.
p.
87.
Griffith, J.
Robins, G.
Salowe, J.S.
and
Tongtong Zhang
1994.
Closing the gap: near-optimal Steiner trees in polynomial time.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 13,
Issue. 11,
p.
1351.
Robins, G.
and
Salowe, J. S.
1995.
Low-degree minimum spanning trees.
Discrete & Computational Geometry,
Vol. 14,
Issue. 2,
p.
151.
Reber, M.
and
Kirsch, A.
1995.
Testability controlled physical design of vertically stacked integrated circuits.
p.
249.
Alexander, M.J.
Cohoon, J.P.
Colflesh, J.L.
Karro, J.
and
Robins, G.
1995.
Three-dimensional field-programmable gate arrays.
p.
253.
Reber, M.
and
Tielert, R.
1996.
Benefits of vertically stacked integrated circuits for sequential logic.
Vol. 4,
Issue. ,
p.
121.
Paul, J.M.
and
Mickle, M.H.
1998.
Three-dimensional computational pipelining with minimal latency and maximum throughput for L-U factorization.
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing,
Vol. 45,
Issue. 11,
p.
1465.
Bollapragada, Rajesh
2004.
Computational Science - ICCS 2004.
Vol. 3039,
Issue. ,
p.
1017.
Pavlidis, Vasilis F.
and
Friedman, Eby G.
2009.
Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits.
Proceedings of the IEEE,
Vol. 97,
Issue. 1,
p.
123.
Pavlidis, Vasilis F.
and
Friedman, Eby G.
2010.
VLSI-SoC: Design Methodologies for SoC and SiP.
Vol. 313,
Issue. ,
p.
1.
Lin, Leo Jyun-Hong
Chang, Hsiao-Pu
Wu, Tzong-Lin
and
Chiou, Yih-Peng
2012.
3D simulation of substrate noise coupling from Through Silicon Via (TSV) and noise isolation methods.
p.
181.
Pangracious, Vinod
Marrakchi, Zied
and
Mehrez, Habib
2015.
Three-Dimensional Design Methodologies for Tree-based FPGA Architecture.
Vol. 350,
Issue. ,
p.
13.