Book contents
- Frontmatter
- Contents
- Preface
- List of gate symbols
- 1 Introduction
- 2 Fault models
- 3 Combinational logic and fault simulation
- 4 Test generation for combinational circuits
- 5 Sequential ATPG
- 6 IDDQ testing
- 7 Functional testing
- 8 Delay fault testing
- 9 CMOS testing
- 10 Fault diagnosis
- 11 Design for testability
- 12 Built-in self-test
- 13 Synthesis for testability
- 14 Memory testing
- 15 High-level test synthesis
- 16 System-on-a-chip test synthesis
- Index
7 - Functional testing
Published online by Cambridge University Press: 05 June 2012
- Frontmatter
- Contents
- Preface
- List of gate symbols
- 1 Introduction
- 2 Fault models
- 3 Combinational logic and fault simulation
- 4 Test generation for combinational circuits
- 5 Sequential ATPG
- 6 IDDQ testing
- 7 Functional testing
- 8 Delay fault testing
- 9 CMOS testing
- 10 Fault diagnosis
- 11 Design for testability
- 12 Built-in self-test
- 13 Synthesis for testability
- 14 Memory testing
- 15 High-level test synthesis
- 16 System-on-a-chip test synthesis
- Index
Summary
In this chapter, we describe functional testing methods which start with a functional description of the circuit and make sure that the circuit's operation corresponds to its description. Since functional testing is not always based on a detailed structural description of the circuit, the test generation complexity can, in general, be substantially reduced. Functional tests can also detect design errors, which testing methods based on the structural fault model cannot.
We first describe methods for deriving universal test sets from the functional description. These test sets are applicable to any implementation of the function from a restricted class of networks.
We then discuss pseudoexhaustive testing of circuits where cones or segments of logic are tested by the set of all possible input vectors for that cone or segment.
Finally, we see how iterative logic arrays can be tested, and how simple design for testability schemes can make such testing easy. We introduce a graph labeling method for this purpose and apply it to adders, multipliers and dividers.
Universal test sets
Suppose the description of a function is given in some form, say a truth table. Consider the case where a fault in the circuit can change the truth table in an arbitrary way. How do we detect all such faults? One obvious way is to apply all 2n vectors to it, where n is the number of inputs.
- Type
- Chapter
- Information
- Testing of Digital Systems , pp. 356 - 381Publisher: Cambridge University PressPrint publication year: 2003
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