Introduction

MIMO techniques play an important role in numerous wireless standards, such as the HSDPA extension of WCDMA, IEEE 802.11n wireless LAN, and IEEE 802.16 wireless MAN. Their success will critically depend on the availability of high-performance, low complexity receivers, which requires careful study of the implementation aspects.

Initially, most efforts toward optimizing MIMO detection for implementations were concerned with highly suboptimal linear and successive interference cancellation (SIC) techniques, since they are associated with the lowest order of complexity. However, as demonstrated recently in a number of application-specific IC (ASIC) implementations, the combination of advances in silicon technology, innovative VLSI architectures, and low complexity algorithms have enabled the implementation of better performing MIMO detection schemes that come closer to realizing the full channel capacity. The highest performing detectors for MIMO systems employ a full maximum likelihood (ML) search of the transmit constellation space. The exhaustive ML approach has been readily demonstrated in implementations for rates up to 8 bits per channel use (bpcu). The problem is that for higher rates, the exhaustive-search ML solution far exceeds current silicon capabilities. Sphere decoding algorithms have emerged as the most promising decoding strategies, providing full, or close to ML, bit error rate (BER) performance at reasonable cost for transmission rates that are relevant in practical systems.

In this chapter, the VLSI implementation aspects of MIMO detection are discussed. First, a general review of the capabilities and limitations of today's silicon technology is presented.