We evaluate the performance of the PLC CSMA/CA protocol by analysis, simulations and testbed measurements. We explain the impact of each parameter on performance and the motivation behind the design choices for PLC. Both throughput and short-term fairness are discussed and modelled. Short-term fairness is achieved when all users share equally the medium over a short time horizon. If short-term fairness is not guaranteed, there exists high delay-deviation that harms certain delay-sensitive ap- plications. We provide fundamental evidence about performance trade- offs of the PLC CSMA/CA. Our study suggests that PLC parameters should be judiciously selected in order to exploit the tradeoff between throughput and fairness and to achieve high QoS for best-effort and delay-sensitive applications. This chapter also presents a cross-layer PHY/MAC evaluation of contending links and investigates the challenges of stations with different rates and hidden terminals.