This chapter, along with the next three, covers the general topic of clock generation and distribution as well as clock and data synchronization. Clocking circuitry, including clock and data recovery systems can dissipate 30–50% of total transceiver power. Jitter degrades BER as much as amplitude noise. Therefore wireline designers must pay attention to the jitter performance of clock generation circuitry and clock distribution circuitry as much as they focus on the amplitude noise behaviour of the receiver’s signal path. Although clock generation can dissipate non-trivial power, the centralized generation of a clean reference clock allows the amortization of its power dissipation across multiple transceiver lanes, although its distribution is also challenging. Therefore, a thorough treatment of all aspects of clocking is important. This chapter gives an overview of the principal synchronization approaches used in wireline systems as well as clock distribution circuitry.