Mixed-Signal CMOS for Wireline Communication Transistor-Level and System-Level Design Considerations
Book contents
- Frontmatter
- Contents
- Preface
- Notation and Acronyms
- 1 Introduction to Wireline Communication
- 2 Electrical Channels
- 3 Decision Circuits
- 4 Equalization
- 5 Electrical-Link Transmitter Circuits
- 6 Electrical-Link Receiver Front-Ends
- 7 Optical Channels and Components
- 8 Optical-Link Transmitter Circuits
- 9 Optical Receivers
- 10 Low-Bandwidth (Equalizer-Based) Optical Receivers
- 11 Advanced Topics in Electrical and Optical Links
- 12 Overview of Synchronization Approaches
- 13 Oscillators
- 14 Phase-Locked Loops and Injection-Locked Oscillators
- 15 Clock and Data Recovery
- Appendix A Frequency Domain Analysis
- Appendix B Noise Analysis
- References
- Index
13 - Oscillators
Published online by Cambridge University Press: 05 December 2024
Book contents
- Frontmatter
- Contents
- Preface
- Notation and Acronyms
- 1 Introduction to Wireline Communication
- 2 Electrical Channels
- 3 Decision Circuits
- 4 Equalization
- 5 Electrical-Link Transmitter Circuits
- 6 Electrical-Link Receiver Front-Ends
- 7 Optical Channels and Components
- 8 Optical-Link Transmitter Circuits
- 9 Optical Receivers
- 10 Low-Bandwidth (Equalizer-Based) Optical Receivers
- 11 Advanced Topics in Electrical and Optical Links
- 12 Overview of Synchronization Approaches
- 13 Oscillators
- 14 Phase-Locked Loops and Injection-Locked Oscillators
- 15 Clock and Data Recovery
- Appendix A Frequency Domain Analysis
- Appendix B Noise Analysis
- References
- Index
Summary
In this chapter we introduce circuits that are used to generate clocks. After an introduction to the metrics of oscillators, this chapter introduces the main categories of oscillators, and how they are made voltage-controlled. The important trade-offs between power, phase-noise, and tuning range are explained. Methods for converting a VCO to a digitally controlled oscillator are included in Section 14.4.
Keywords
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- Chapter
- Information
- Mixed-Signal CMOS for Wireline CommunicationTransistor-Level and System-Level Design Considerations, pp. 308 - 332Publisher: Cambridge University PressPrint publication year: 2024