Digitally-assisted design of data converters

doi:10.1017/CBO9781316156148.006

5 - Digitally-assisted design of data converters

Published online by Cambridge University Press: 05 August 2015

Yun Chiu

Edited by

Xicheng Jiang

Show author details

Yun Chiu: Affiliation:
The University of Texas at Dallas, Dallas, Texas, USA
Xicheng Jiang: Affiliation:
Broadcom, Irvine

Book contents

Get access

Summary

In this chapter, the recent trend of addressing a few challenging technical aspects of analog-to-digital converter (ADC) design using digital assistance is explored. In our viewpoint, digital assistance is a term evolved and directly descended from the conventional concept of digital calibration. The slight distinction between the two perhaps resides in the fact that the latest development of the technique is more focused on the so-called background treatment whereas earlier works often referred to a foreground case. Limited by the number of pages, this chapter will be dedicated to narrating the background digital techniques for enhancing raw analog performance metrics such as component matching, circuit linearity, and timing accuracy. As case studies, the converters discussed in this chapter include the pipeline and successive-approximation types. It is the goal to establish that digital assistance, when properly deployed, can help relax certain demanding aspects of an analog design, reduce the designers’ effort, and/or improve the power efficiency of the design.

We also point out that while it is true that a converter circuit is simplified in the conventional sense with digital assistance, one needs to recognize that the design complexity now is shifted to the system level – the design and verification of the digital algorithm that has to be integrated into the digital part of the converter or off-loaded to an external DSP or FPGA unit. In many cases, the background nature of the treatment requires billions or trillions of clock cycles for full verification of an algorithm, which can result in a significant bottleneck for the design process. In addition, the conception and design of the adaptive algorithms employed in digital assistance dictates knowledge and expertise outside the realm of conventional analog design. Thus, while the chips are becoming adaptive, the analog designers perhaps need to adapt along with the evolution of the technology and design arts.

Overview and historic remarks

5..1.1 Background vs. foreground calibration

In general, digital assistance is defined as the post-fabrication procedures of trimming, tuning, and/or reconfiguration of analog, mixed-signal (MS), and/or radio-frequency (RF) integrated circuits (IC) or post-processing of circuit outputs via digital means to obtain difficult- or expensive-to-obtain performance metrics with raw circuits. In general, it can be administered one time (e.g., during chip testing at either wafer or package level), occasionally (e.g., during circuit power-up or idle times), or in situ during the normal operation of the circuits.

Type: Chapter
Information: Digitally-Assisted Analog and Analog-Assisted Digital IC Design , pp. 135 - 173

DOI: https://doi.org/10.1017/CBO9781316156148.006 [Opens in a new window]

Publisher: Cambridge University Press

Print publication year: 2015

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Book purchase

Temporarily unavailable

References

[1] McNeill, J. A., Coln, M. C. W., and Larivee, B. J., “‘Split ADC’ architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2437–2445, 2005.CrossRef Google Scholar

[2] Boyacigiller, Z. G., Weir, B., and Bradshaw, P. D., “An error-correcting 14b/20μs CMOS A/D converter,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 62–63, 1981.

[3] Karanicolas, N. and Lee, H.-S., “A 15-b 1-MS/s digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207–1215, 1993.CrossRef Google Scholar

[4] Poulton, K., Neff, R., Setterberg, B., et al., “A 20 GS/s 8 b ADC with a 1 MB memory in 0.18μm CMOS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2003, pp. 318–319.

[5] Der, L. and Razavi, B., “A 2 GHz CMOS image-reject receiver with sign-sign LMS calibration,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2001, pp. 294–295.

[6] Lee, H.-S., Hodges, D., and Gray, P. R., “A self-calibrating 15 bit CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 813–819, 1984.CrossRef Google Scholar

[7] Moon, U.-K. and Song, B.-S., “Background digital calibration techniques for pipelined ADCs,” IEEE Trans. Circuits and Systems II, vol. 44, no. 2, pp. 102–109, 1997.Google Scholar

[8] Kwak, S.-U., Song, B.-S., and Bacrania, K., “A 15-b, 5-Msample/s low-spurious CMOS ADC,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1866–1875, 1997.CrossRef Google Scholar

[9] Ingino, J. M. and Wooley, B. A., “A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1920–1931, 1998.CrossRef Google Scholar

[10] Dyer, K. C., Fu, D., Lewis, S. H., and Hurst, P. J., “An analog background calibration technique for time-interleaved analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1912–1919, 1998.CrossRef Google Scholar

[11] Erdogan, O. E., Hurst, P. J., and Lewis, S. H., “A 12-b digital-background-calibrated algorithmic ADC with –90-dB THD,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1812–1820, 1999.CrossRef Google Scholar

[12] Blecker, E. B., McDonald, T. M., Erdogan, O. E., Hurst, P. J., and Lewis, S. H., “Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1059–1062, 2003.CrossRef Google Scholar

[13] Grace, C., Hurst, P. J., and Lewis, S. H., “A 12b 80MS/s pipelined ADC with bootstrapped digital calibration,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038–1046, 2005.CrossRef Google Scholar

[14] Roberts, L. G., “Picture coding using pseudo-random noise,” IRE Trans. Inform. Theory, vol. IT-8, pp. 145–154, Feb. 1962.CrossRef Google Scholar

[15] Jewett, R., Poulton, K., Hsieh, K.-C., and Doemberg, J., “A 12b 128MS/s ADC with 0.05LSB DNL,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 1997, pp. 138–139.

[16] Fetterman, H. S., Martin, D. G., and Rich, D. A., “CMOS pipelined ADC employing dither to improve linearity,” in Proc. IEEE Custom Integrated Circuits Conf., 1999, pp. 109–112.

[17] Wiesbauer, A. and Temes, G. C., “Adaptive compensation of analog circuit imperfections for cascaded sigma-delta modulators,” inProc. Asilomar Conf. Circuits, Systems and Computers, vol. 2, 1996, pp. 1073–1077.Google Scholar

[18] Petrie, C. and Miller, M., “A background calibration technique for multibit delta-sigma modulators,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 2, 2000, pp. 29–32.Google Scholar

[19] Sun, T., Wiesbauer, A., and Temes, G. C., “Adaptive compensation of analog circuit imperfections for cascaded delta-sigma ADCs,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, 1998, pp. 405–407.Google Scholar

[20] Kiss, P., Silva, J., Wiesbauer, A., et al., “Adaptive digital correction of analog errors in MASH ADCs—Part II: Correction using test-signal injection,” IEEE Trans. Circuits and Systems II, vol. 47, no. 7, pp. 629–638, 2000.CrossRef Google Scholar

[21] Fu, D., Dyer, K. C., Lewis, S. H., and Hurst, P. J., “A digital background calibration technique for time-interleaved analog-to-digital converters,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1904–1911, 1998.Google Scholar

[22] Ming, J. and Lewis, S. H., “An 8 b 80 Msample/s pipelined ADC with background calibration,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2000, pp. 42–43.

[23] Siragusa, E. and Galton, I., “Gain error correction technique for pipelined analogue-to-digital converters,” Electronics Letters, vol. 36, no. 7, pp. 617–618, 2000.CrossRef Google Scholar

[24] Galton, I., “Digital cancellation of D/A converter noise in pipelined A/D converters,” IEEE Trans. Circuits and Systems II, vol. 47, no. 3, pp. 185–196, 2000.CrossRef Google Scholar

[25] Yu, P. C., Shehata, S., Joharapurkar, A., et al., “A 14b 40MSample/s pipelined ADC with DFCA,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2001, pp. 136–137.

[26] Siragusa, E. and Galton, I., “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2126–2138, 2004.CrossRef Google Scholar

[27] Liu, H.-C., Lee, Z.-M., and Wu, J.-T., “A 15b 20MS/s CMOS pipelined ADC with digital background calibration,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2004, pp. 454–455.

[28] Nair, K. and Harjani, R., “A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2004, pp. 456–457.

[29] Massolini, R., Cesura, G., and Castello, R., “A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC,” IEEE Trans. Circuits and Systems II, vol. 53, no. 5, pp. 389–393, 2006.CrossRef Google Scholar

[30] Shu, Y.-S. and Song, B.-S., “A 15b linear, 20MS/s, 1.5b/stage pipelined ADC digitally calibrated with signal-dependent dithering,” in IEEE Symp. VLSI Circuits, Dig. Tech. Papers, 2006, pp. 218–219.

[31] Panigada, A. and Galton, I., “Digital background correction of harmonic distortion in pipelined ADCs,” IEEE Trans. Circuits and Systems I, vol. 53, no. 9, pp. 1885–1895, 2006.CrossRef Google Scholar

[32] Panigada, A. and Galton, I., “A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2009, pp. 162–163.

[33] Murmann, B. and Boser, B., “A 12b 75MS/s pipelined ADC using open-loop residue amplification,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2003, pp. 328–329.

[34] Li, J. and Moon, U.-K., “Background calibration techniques for multistage pipelined ADCs with digital redundancy,” IEEE Trans. Circuits and Systems II, vol. 50, no. 9, pp. 531–538, 2003.Google Scholar

[35] Keane, J. P., Hurst, P. J., and Lewis, S. H., “Background interstage gain calibration technique for pipelined ADCs,” IEEE Trans. Circuits and Systems I, vol. 52, no. 1, pp. 32–43, 2005.CrossRef Google Scholar

[36] Chiu, Y., Lee, S.-C., and Liu, W., “An ICA framework for digital background calibration of analog-to-digital converters,” Sampling Theory in Signal and Image Processing, vol. 11, no. 2–3, pp. 253–270, 2012.Google Scholar

[37] Liu, W., Huang, P., and Chiu, Y., “A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration,” in Proc. IEEE Custom Integrated Circuits Conf., 2012, pp. 1–4.

[38] Lee, S.-C. and Chiu, Y., “Digital calibration of nonlinear memory errors in sigma-delta modulators,” IEEE Trans. Circuits and Systems I, vol. 57, no. 9, pp. 2462–2475, 2010.CrossRef Google Scholar

[39] Lee, S.-C. and Chiu, Y., “A 15-MHz bandwidth 1–0 MASH SD ADC with nonlinear memory error calibration achieving 85-dBc SFDR,” IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 695–707, 2014.CrossRef Google Scholar

[40] Wang, X., Hurst, P. J., and Lewis, S. H., “A 12-bit 20-MS/s pipelined ADC with nested digital background calibration,” in Proc. IEEE Custom Integrated Circuits Conf., 2003, pp. 409–412.

[41] Chiu, Y., Tsang, C. W., Nikolic, B., and Gray, P. R., “Least-mean-square adaptive digital background calibration of pipelined analog-to-digital converters,” IEEE Trans. Circuits and Systems I, vol. 51, no. 1, pp. 38–46, 2004.CrossRef Google Scholar

[42] Liu, W., Chang, Y., Hsien, S.-K., et al., “A 600MS/s 30mW 0.13μm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2009, pp. 82–83.

[43] McNeill, J. A., David, C., Coln, M., and Croughwell, R., “‘Split ADC’ calibration for all-digital correction of time-interleaved ADC errors,” IEEE Trans. Circuits and Systems II, vol. 56, no. 5, pp. 344–348, 2009.Google Scholar

[44] Peng, B., Li, H., Lee, S.-C., Lin, P., and Chiu, Y., “A virtual-ADC digital background calibration technique for multistage A/D conversion,” IEEE Trans. Circuits and Systems II, vol. 57, no. 11, pp. 853–857, 2010.Google Scholar

[45] Lewis, S., Fetterman, H. S., Gross, G. F., Ramachandran, R., and Viswanathan, T. R., “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351–358, 1992.CrossRef Google Scholar

[46] Mayes, M. K. and Chin, S. W., “A 200-mW, 1-Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1862–1872, 1996.CrossRef Google Scholar

[47] Iroaga, E. and Murmann, B., “A 12-bit 75-MS/s pipelined ADC using incomplete settling,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 748–756, 2007.CrossRef Google Scholar

[48] Keane, J. P., Hurst, P. J., and Lewis, S. H., “Digital background calibration for memory effects in pipelined analog-to-digital converters,” IEEE Trans. Circuits and Systems I, vol. 53, no. 3, pp. 511–525, 2006.CrossRef Google Scholar

[49] Chen, C.-Y. and Wu, J., “A 12-bit 3 GS/s pipeline ADC with 500 mW and 0.4 mm2 and 500 mW in 40 nm digital CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 1013–1021, 2012.CrossRef Google Scholar

[50] Peng, B., Li, H., Lin, P., and Chiu, Y., “An offset double conversion technique for digital calibration of pipelined ADCs,” IEEE Trans. Circuits and Systems II, vol. 57, no. 12, pp. 961–965, 2010.Google Scholar

[51] Stepanovic, D. and Nikolic, B., “A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS,” in IEEE Symp. VLSI Circuits, Dig. Tech. Papers, 2012, pp. 84–85.

[52] Zhang, M. M., Hurst, P. J., Levy, B. C., and Lewis, S. H., “Gain-error calibration of a pipelined ADC in an adaptively equalized baseband receiver,” IEEE Trans. Circuits and Systems II, vol. 56, no. 10, pp. 768–772, 2009.CrossRef Google Scholar

[53] Widrow, B. and Stearns, S. D., Adaptive Signal Processing. Prentice Hall, 1985.Google Scholar

[54] Haykin, S., Adaptive Filter Theory, Prentice Hall, 1996.Google Scholar

[55] Xu, B. and Chiu, Y., “Background calibration of time-interleaved ADC using direct derivative information,” in Proc. IEEE Int. Symp. Circuits and Systems, 2013, pp. 2456–2459.

[56] Tsang, C., Chiu, Y., Vanderhaegen, J., et al., “Background ADC calibration in digital domain,” in Proc. IEEE Custom Integrated Circuits Conf., 2008, pp. 301–304.

[57] Sarkar, S., Zhou, Y., Elies, B., and Chiu, Y., “PN-assisted deterministic digital background calibration of multistage split-pipelined ADC,” IEEE Trans. Circuits and Systems I, 2015, in press.

[58] McCreary, J. L. and Gray, P. R., “All-MOS charge redistribution analog-to-digital conversion techniques–Part I,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp. 371–379, 1975.CrossRef Google Scholar

[59] Kuttner, F., “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2002, pp. 176–177.

[60] Liu, C. C., Chang, S.-J., Huang, G.-Y.et al., “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2010, pp. 386–387.

[61] Liu, W., Huang, P., and Chiu, Y., “A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2010, pp. 380–381.

[62] Hurrell, C. P., Lyden, C., Laing, D., Hummerston, D., and Vickery, M., “An 18b 12.5MS/s ADC with 93dB SNR,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2647–2654, 2010.CrossRef Google Scholar

[63] Wei, H., Chan, C.-H., Chio, U-F., et al., “A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2011, pp. 188–190.

[64] Zhu, Y., Chan, C.-H., Sin, S.-W., Swname, S.-P.U, and Martins, R. P., “A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC,” in IEEE Symp. VLSI Circuits, Dig. Tech. Papers, 2012, pp. 90–91.

[65] Wang, G., Kacani, F., and Chiu, Y., “IRD digital background calibration of SAR ADC with coarse reference ADC acceleration,” IEEE Trans. Circuits and Systems II, vol. 61, no. 1, pp. 11–15, 2014.Google Scholar

[66] Chiu, Y., Kacani, F., Huang, P., and Liu, W., “A digitally calibrated 14-bit 36-MS/s 65-nm CMOS SAR ADC with redundant double conversion,” in Proc. IEEE Int. Conf. Solid-State and Integrated-Circuit Tech., 2014.

[67] Draxelmayr, D., “A self-calibration technique for redundant A/D converters providing 16b accuracy,” in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 1988, pp. 204–205.