In this chapter we investigate hardware implementation of the DDS, sinusoidal and arbitrary waveform generation techniques presented in earlier chapters. We do not concern ourselves with specific target technologies such as FPGAs, but restrict our signal flow descriptions to the ‘register transfer level’ (RTL). The exact implementation technology (e.g. FPGA, ASIC or even hardwired logic) and the partitioning between hardware and embedded software are left to the suitably skilled reader and his or her application-specific requirements. For the most part, implementation of these algorithms, particularly in wide bandwidth applications, is best handled in high speed FPGA or ASIC logic. It is intended that this chapter will impart sufficient architectural detail to enable adaptation to any particular implementation technology.

There are several processing strategies that underpin high speed DSP hardware implementation. These comprise arithmetic pipelining, time division multiplexing and parallel processing. We begin Section 8.1 by reviewing these techniques. We then discuss high speed pipelined implementation of the digital accumulator and its constituent adder which are fundamental building blocks in both DDS and the IDFT. Given its fundamental importance, we investigate wavetable memory architectures and introduce the idea of a ‘vector memory’ that produces a vector of consecutive data samples relative to a single base address in only one memory access cycle. This architecture employs a combination of parallel processing and pipelining. As we recall from Chapter 5, phase interpolated wavetable indexing requires multiple wavetable samples that surround the sample indexed by the integer part of the fractional phase index. The number of samples, and hence the length of the vector, are determined by the order of the interpolation polynomial.