Book contents
- Frontmatter
- Contents
- Contributors
- Preface
- Section I CMOS circuits and technology limits
- Section II Tunneling devices
- 5 Designing a low-voltage, high-current tunneling transistor
- 6 Tunnel transistors
- 7 Graphene and 2D crystal tunnel transistors
- 8 Bilayer pseudospin field effect transistor
- Section III Alternative field effect devices
- Section IV Spin-based devices
- Section V Interconnect considerations
- Index
- References
6 - Tunnel transistors
from Section II - Tunneling devices
Published online by Cambridge University Press: 05 February 2015
- Frontmatter
- Contents
- Contributors
- Preface
- Section I CMOS circuits and technology limits
- Section II Tunneling devices
- 5 Designing a low-voltage, high-current tunneling transistor
- 6 Tunnel transistors
- 7 Graphene and 2D crystal tunnel transistors
- 8 Bilayer pseudospin field effect transistor
- Section III Alternative field effect devices
- Section IV Spin-based devices
- Section V Interconnect considerations
- Index
- References
Summary

- Type
- Chapter
- Information
- CMOS and BeyondLogic Switches for Terascale Integrated Circuits, pp. 117 - 143Publisher: Cambridge University PressPrint publication year: 2015
References
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