Skip to main content Accessibility help

We use cookies to distinguish you from other users and to provide you with a better experience on our websites. Close this message to accept cookies or find out how to manage your cookie settings.

Close cookie message
×
Hostname: page-component-669899f699-g7b4s Total loading time: 0 Render date: 2025-04-30T05:50:59.437Z Has data issue: false hasContentIssue false

15 - Interconnect considerations

from Section V - Interconnect considerations

Published online by Cambridge University Press:  05 February 2015

By
Shaloo Rakheja ,
Ahmet Ceyhan  and
Azad Naeemi
Edited by
Tsu-Jae King Liu  and
Kelin Kuhn
Shaloo Rakheja
Affiliation:
Massachusetts Institute of Technology
Ahmet Ceyhan
Affiliation:
Georgia Institute of Technology
Azad Naeemi
Affiliation:
Georgia Institute of Technology
Tsu-Jae King Liu
Affiliation:
University of California, Berkeley
Kelin Kuhn
Affiliation:
Cornell University, New York
Get access

Summary

Introduction

The exponential growth of the electronics industry has been guided by the continual reduction in feature size of microchips manufactured using silicon-based CMOS technology. This reduction in feature size, commonly known as dimensional scaling, has enabled significant improvements in transistor performance and power – a higher transistor density for improved functionality, complexity, and performance of microchips; and a reduction in the cost per function. These benefits have enabled the semiconductor industry to offer a wide range of new products at every technology generation.

The research pipeline of the semiconductor industry involves increasingly radical potential solutions to carry technology advancement through dimensional scaling to beyond the 10-year visibility limit. Many logic devices that require innovations in materials, use of heterogeneous technologies, and the exploitation of alternative state variables and non-binary computation schemes are under investigation to extend Moore’s law to beyond the year 2020. These logic devices differ in structure and operating principles, and include various physical quantities that may be used for encoding information, such as charge, electric dipole, magnetic dipole (spin), orbital state, mechanical position, light intensity, etc.

Besides smaller and faster transistors, the semiconductor industry requires fast and dense interconnects to manufacture high-performance microchips. The evolution of integrated circuits from an embedded system of only a few components to large-scale systems with billions of devices transformed the interconnection problem into one of the major threats to continue improving the performances of microchips at each new technology node [1]. Interconnects impose major limits on the performance of integrated circuits because of the delay they add to critical paths, the energy they dissipate, the noise and jitter they induce, and the degrading metal and dielectric reliability due to vulnerability to electromigration (EM) and time-dependent dielectric breakdown (TDDB), respectively. All of these limitations worsen with dimensional scaling.

Type
Chapter
Information
CMOS and Beyond
Logic Switches for Terascale Integrated Circuits
 , pp. 381 - 412
Publisher: Cambridge University Press
Print publication year: 2015

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Book purchase

Temporarily unavailable

References

Bohr, M. T., “Interconnect scaling – the real limiter to high performance ULSI.” Electron Devices Meeting (IEDM), 1995 IEEE International, pp. 241–244 (1995).
International Technology Roadmap for Semiconductors (ITRS) (2012). Available at: .
Bakoglu, H. B. & Meindl, J. D., “Optimal interconnection networks for ULSI.” IEEE Transactions Electron Devices, 32(5), 903–909 (1985).CrossRefGoogle Scholar
Young, I. & Raol, K., “A comprehensive metric for evaluating interconnect performance.” Interconnect Technology Conference, 2001 IEEE International, pp. 119–121 (2001).
Baliga, J., “Chips go vertical [3D IC interconnection].” IEEE Spectrum, 41(3), 43–47 (2004).CrossRefGoogle Scholar
Ceyha, A. & Naeemi, A., “Multilevel interconnect networks for the end of the roadmap: conventional Cu/low-k and emerging carbon based interconnects.” In Interconnect Technology Conference, IEEE International, pp. 1–3 (2011).
Bakoglu, H. B., Circuits, Interconnections and Packaging for VLSI (Reading, MA, Addison-Wesley, 1990).Google Scholar
Davis, J. A., Venkatesan, R. et al., “Interconnect limits on gigascale integration (GSI) in the 21st century.” Proceedings of the IEEE, 89(3), 305–324 (2001).CrossRefGoogle Scholar
Mathon, J. & Umerski, A., “Theory of tunneling magnetoresistance of an epitaxial Fe/MgO/Fe(001) junction.” Physical Review B, 63(22) (2001).CrossRefGoogle Scholar
Meindl, J. D., Venkatesan, R. et al., “Interconnecting device opportunities for gigascale integration (GSI).” In Electron Devices Meeting, IEEE International, pp. 23.21.21–23.21.24 (2001).
Meindl, J. D., Davis, J. A. et al., “Interconnect opportunities for gigascale integration.” IBM Journal of Research and Development, 46(2–3), 245–263 (2002).CrossRefGoogle Scholar
Edelstein, D., Heidenreich, J. et al. “Full copper wiring in a sub-0.25mum CMOS ULSI technology.” In Electron Devices Meeting, 1997 IEEE International, pp. 773–776 (1997).
Bohr, M., “The new era of scaling in an SoC world.” In Solid-State Conference, 2009 IEEE International, Digest of Technical Papers, pp. 23–28 (2009).
Borkar, S., “A thousand core chips.” In Proceedings of the 44th Annual Design Automation Conference (DAC) (2007).
Davis, W. R., Wilson, J. et al., “Demystifying 3D ICs: the pros and cons of going vertical.” IEEE Design and Test of Computers, 22(6), 498–510 (2005).CrossRefGoogle Scholar
Beausoleil, R. G., Kuekes, P. J. et al., “Nanoelectronic and nanophotonic interconnect.” Proceedings of the IEEE, 96(2), 230–247 (2008).CrossRefGoogle Scholar
Krishnamoorthy, A. V., Ho, R. et al. “Computer systems based on silicon photonic interconnects.” Proceedings of the IEEE, 97(7), 1337–1361 (2009).CrossRefGoogle Scholar
Balakrishnan, A., “Analysis and Optimization of Global Interconnects for Many-core Architectures.” Department of Electrical and Computer Engineering. Atlanta, GA, Georgia Institute of Technology. MS (2010).Google Scholar
Guillaumond, J. F., Arnaud, L. et al., “Analysis of resistivity in nano-interconnect: full range (4.2–300 K) temperature characterization.” In Interconnect Technology Conference, 2003 International, pp. 132–134 (2003).
Besling, W. F. A., Broekaart, M. et al., “Line resistance behavior in narrow lines patterned by a TiN hard mask spacer for 45 nm node interconnects.” Microelectronic Engineering, 76(1–4), 167–174 (2004).CrossRefGoogle Scholar
Steinhoegl, W., Schindler, G. et al., “Impact of line edge roughness on the resistivity of nanometer-scale interconnects.” Microelectronic Engineering, 76(1–4), 126–130 (2004).CrossRefGoogle Scholar
Steinhoegl, W., Schindler, G. et al., “Unraveling the mysteries behind size effects in metallization systems.” Semiconductor International, 28, 34–38 (2005).Google Scholar
Steinhoegl, W., Schindler, G. et al., “Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller.” Journal of Applied Physics, 97(2), 023701–023707 (2005).Google Scholar
Chen, H.-C., Chen, H.-W. et al., “Resistance increase in metal-nanowires.” In VLSI Technology, Systems, and Applications, International Symposium on, pp. 1–2 (2006).
Plombon, J. J., Andideh, E. et al., “Influence of phonon, geometry, impurity, and grain size on copper line resistivity.” Applied Physics Letters, 89(11), 113123–113124 (2006).CrossRefGoogle Scholar
Shimada, M., Moriyama, M. et al., “Electrical resistivity of polycrystalline Cu interconnects with nano-scale linewidth.” Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 24(1), 190–194 (2006).CrossRefGoogle Scholar
Kitada, H., Suzuki, T. et al., “The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology.” In Interconnect Technology Conference, International, pp. 10–12 (2007).
Nagaraj, N. S., Hunter, W. R. et al., “Impact of interconnect technology scaling on SoC design methodologies.” In International Interconnect Technology Conference, pp. 71–73 (2005).
Kaloyeros, A., Eisenbraun, E. T. et al., “Zero thickness diffusion barriers and metallization liners for nanoscale device applications.” Chemical Engineering Communications, 198(11), 1453–1481 (2011).CrossRefGoogle Scholar
Sinha, S., Yeric, G. et al., “Exploring sub-20-nm finFET design with predictive technology models.” In Design Automation Conference (DAC), pp. 283–288 (2012).
Magen, N., Kolodny, A. et al., “Interconnect-power dissipation in a microprocessor.” In International Workshop on System Level Interconnect Prediction (SLIP) (2004).
Wang, X., Ouyang, Y. et al., “Room-temperature all-semiconducting sub-10-nm graphene nanoribbon field-effect transistors.” Physics Review Letters, 100(20), 206803 (2008).CrossRefGoogle ScholarPubMed
Deng, J. & Wong, H.-S. P., “A compact SPICE model for carbon nanotube field-effect transistors including non-idealities and its application part 1: model of the intrinsic channel region.” IEEE Transactions Electron Devices, 54(12), 3186–3194 (2007).CrossRefGoogle Scholar
Seabaugh, A. C. & Zhang, Q., “Low-voltage tunnel transistors for beyond CMOS logic.” Proceedings of the IEEE 98(12), 2095–2110 (2008).CrossRefGoogle Scholar
Luisier, M., & Klimeck, G., “Atomistic full-band design study of InAs band-to-band tunneling field-effect transistors.” IEEE Electron Devices Letters, 30(6), 602–604 (2009).CrossRefGoogle Scholar
Zhirnov, V. V., Cavin, III R. K. et al., “Limits to binary logic switch scaling – a gedanken model.” Proceedings of the IEEE 91(11), 1934–1939 (2003).CrossRefGoogle Scholar
Galatsis, K., Khitun, A. et al., “Alternate state variables for emerging nanoelectronic devices.” IEEE Transactions on Nanotechnology, 8(1), 66–75 (2009).CrossRefGoogle Scholar
Rakheja, S. & Naeemi, A., “Interconnects for novel state variables: physical limits and device and circuit implications.” IEEE Transactions on Electron Devices, 57(10) (2010).CrossRefGoogle Scholar
Rakheja, S. & Naeemi, A., “Communicating novel computational state variables: post-CMOS logic.” IEEE Nanotechnology, 7, 15–23 (2013).CrossRefGoogle Scholar
Nikonov, D., & Bourianoff, G., “Operation and modeling of semiconductor spintronics computing devices.” Journal of Superconductivity and Novel Magnetism, 21(8), 479–493 (2008).CrossRefGoogle Scholar
Cahay, M. & Bandyopadhyay, S., “An electron’s spin – part I.” Potentials, IEEE, 28(3), 31–35 (2009).CrossRefGoogle Scholar
Sughara, S., “Spin-transistor electronics: an overview and outlook.” Proceedings of the IEEE, 98(12), 2124–2154 (2010).CrossRefGoogle Scholar
Gruenberg, P., Schreiber, R. et al., “Layered magnetic structures: evidence for antiferromagnetic coupling of Fe layers across Cr interlayers.” Physical Review Letters, 57 (1986).Google Scholar
Moodera, J., Kinder, L. et al., “Large magnetoresistance at room temperature in ferromagnetic thin film tunnel junctions.” Physical Review Letters, 74, 3273–3276 (1995).CrossRefGoogle ScholarPubMed
Julliere, M., “Tunneling between ferromagnetic films.” Physics Letters A, 54, 225–226 (1975).CrossRefGoogle Scholar
Yuasa, S., Nagahama, T. et al., “Giant room-temperature magnetoresistance in single crystal Fe/Mgo/Fe magnetic tunnel junctions.” Nature Materials 3(12), 868–871 (2004).CrossRefGoogle ScholarPubMed
Daughton, J. M., “Magnetic tunneling applied to memory.” Journal of Applied Physics, 81(8), 3758–3763 (1997).CrossRefGoogle Scholar
Tehrani, S., Slaughter, J. M. et al., “Magnetoresistive random access memory using magnetic tunnel junctions.” Proceedings of the IEEE, 91(5), 703–714 (2003).CrossRefGoogle Scholar
Jian-Gang, Z., “Magnetoresistive random access memory: the path to competitiveness and scalability.” Proceedings of the IEEE, 96(11), 1786–1798 (2008).CrossRefGoogle Scholar
Datta, S., & Das, B., “Electronic analog of the electro-optic modulator.” Applied Physics Letters, 56(7), 665–667 (1990).CrossRefGoogle Scholar
Johnson, M., “Bipolar spin switch.” Science, 260(5106), 320–323 (1993).CrossRefGoogle ScholarPubMed
Johnson, M., “The bipolar spin transistor.” Nanotechnology, 7(4), 390–396 (1996).CrossRefGoogle Scholar
Behin-Aein, B., Datta, D. et al., “Proposal for an all-spin logic device with built in memory.” Nature Nanotechnology, 5, 266–270 (2010).CrossRefGoogle ScholarPubMed
Khitun, A., Bao, M. et al., “Spin wave logic circuit on silicon platform.” In Information Technology: New Generations, ITNG 2008, Fifth International Conference on (2008).
Khitun, A., & Wang, K. L., “Nano scale computational architectures with spin wave bus.” Superlattices and Microstructures, 38(3), 184–200 (2005).CrossRefGoogle Scholar
Khitun, A., Nikonov, D. E. et al., “Feasibility study of logic circuits with a spin wave bus.” Nanotechnology, 18(46) (2007).CrossRefGoogle ScholarPubMed
Liu, L., Lee, O. J. et al., “Magnetic switching by spin torque from the spin Hall effect.” arXiv:1110.6846 (2012).
Liu, L., Pai, C.-F. et al., “Spin torque switching with the giant spin Hall effect of tantalum.” Science, 336 (2012).CrossRefGoogle ScholarPubMed
Sun, J. Z., Gaidis, M. C. et al., “A three-terminal spin-torque-driven magnetic switch.” Applied Physics Letters, 95, 083506 (2009).CrossRefGoogle Scholar
Pai, C.-F., Liu, L., et al., “Spin transfer torque devices utilizing the giant spin Hall effect of tungsten.” Applied Physics Letters, 101 (2012).CrossRefGoogle Scholar
Elliott, R. J., “Theory of the effect of spin-orbit coupling on magnetic resonance in some semiconductors.” Physical Review, 96(2), 14 (1954).CrossRefGoogle Scholar
Lepine, D. J., “Spin resonance of localized and delocalized electrons in phosphorus-doped silicon between 20K and 300K.” Physical Review B, 2 (1970).CrossRefGoogle Scholar
Cheng, J., Wu, M. et al., “Theory of the spin relaxation of conduction electrons in silicon.” Physical Review Letters, 104(1) (2010).CrossRefGoogle ScholarPubMed
Restrepo, O. D. & Windl, W., “Full first-principles theory of spin relaxation in group-IV materials.” Physics Review Letters, 109, 166604 (2012).CrossRefGoogle ScholarPubMed
Kodera, H., “Effect of doping on the electron spin resonance in phosphorus doped silicon.” Journal of the Physical Society of Japan, 19(6) (1964).Google Scholar
Kodera, H., “Effect of doping on the electron spin resonance in phosphorus doped silicon. II.” Journal of the Physical Soceity of Japan, 21(6) (1966).Google Scholar
Kodera, H., “Effect of doping on the electron spin resonance in phosphorus doped silicon. III. Absorption intensity.” Journal of the Physical Society of Japan, 26, 377–380 (1969).CrossRefGoogle Scholar
Kodera, H., “Dyson effect in the electron spin resonance of phosphorus-doped silicon.” Journal of the Physical Society of Japan, 28, 89–98 (1970).CrossRefGoogle Scholar
Fabian, J., Matos-Abiague, A. et al., “Semiconductor spintronics.” Acta Physica Slovaca, 57(4 & 5) (2007).Google Scholar
Pikus, G. E. & Titkov, A. N., Chapter 3, in Optical Orientation, ed. Meier, F. and Zakharchenya, B. P. (Amsterdam: North-Holland, 1984).Google Scholar
Bungay, A., Popov, S. et al., “Direct measurement of carrier spin relaxation times in opaque solids using the specular inverse Faraday effect.” Physics Letters A, 234 (1997).CrossRefGoogle Scholar
Kimel, A., Bentivegna, F. et al., “Room-temperature ultrafast carrier and spin dynamics in GaAs probed by the photoinduced magneto-optical Kerr effect.” Physical Review B, 63(23) (2001).CrossRefGoogle Scholar
Garzon, S., Zutic, I. et al., “Temperature-dependent asymmetry of the nonlocal spin-injection resistance: evidence for spin nonconserving interface scattering.” Physical Review Letters, 94(17) (2005).CrossRefGoogle ScholarPubMed
Yang, T., Kimura, T. et al., “Giant spin-accumulation signal and pure spin-current-induced reversible magnetization switching.” Nature Physics, 4(11), 851–854 (2008).CrossRefGoogle Scholar
Zou, H., Wang, X. J. et al., “Reduction of spin-flip scattering in metallic nonlocal spin valves.” Journal of Vacuum Science & Technology B 28(6) (2010).CrossRefGoogle Scholar
Poli, N., Urech, M. et al., “Spin-flip scattering at Al surfaces.” Journal of Applied Physics, 99(8) (2006).CrossRefGoogle Scholar
Jedema, F. J., Nijboer, M. S. et al., “Spin injection and spin accumulation in all-metal mesoscopic spin valves.” Physical Review B, 2003(67) (2003).Google Scholar
Tombros, N., Tanabe, S. et al., “Anisotropic spin relaxation in graphene.” Physical Review Letters, 101(4), 4 (2008).CrossRefGoogle ScholarPubMed
Popinciuc, M., Zsa, C. J. et al., “Electronic spin transport in graphene field effect transistors.” Physics Reviews B, 80, 214427 (2009).CrossRefGoogle Scholar
Wojtaszek, M., Vera-Marun, I. J. et al., “Enhancement of spin relaxation time in hydrogenated graphene spin-valve devices.” Physical Review B 87(8), 5 (2013).CrossRefGoogle Scholar
Huertas-Hernando, D., “Spin relaxation times in disordered graphene.” The European Physical Journal, 148(1), 177–181 (2007).Google Scholar
Zhang, P. & Wu, M. W., “Electron spin relaxation in graphene with random rashba field: comparison of d’Yakonov–Perel and Elliott–Yafet-like mechanisms.” New Journal of Physics 14(March) (2012).CrossRefGoogle Scholar
Bass, J., & Pratt, W. P., “Spin-diffusion lengths in metals and alloys, and spin-flipping at metal/metal interfaces: an experimentalist’s critical review.” Journal of Physics: Condensed Matter, 19 (2007).Google Scholar
Yu, Z. & Flatte, M., “Spin diffusion and injection in semiconductor.” Physical Review B 66, 14 (2002).Google Scholar
Rakheja, S. & Naeemi, A., “Roles of doping, temperature, and electric field on spin transport through semiconducting channels in spin valves.” IEEE Transactions on Nanotechnology, 12(5), 796–805 (2013).CrossRefGoogle Scholar
Rakheja, S. & Naeemi, A., “Interconnect analysis in spin-torque devices: Performance modeling, optimal repeater insertion, and circuit-size limits.” In Quality Electronic Design, 2012 13th International Symposium on, pp. 283–290 (2012).
Roy, K., Bandyopadhyay, S. et al., “Hybrid spintronics and straintronics: A magnetic technology for ultra low energy computing and signal processing.” Applied Physics Letters, 99(6), 3 (2011).CrossRefGoogle Scholar
Bennett, C. H., “The thermodynamics of computation – a review.” International Journal of Theoretical Physics, 21(12), 905–940 (1982).CrossRefGoogle Scholar
Fashami, M. S., Roy, K. et al., “Magnetization dynamics, Bennett clocking and associated energy dissipation in multiferroic logic.” Nanotechnology, 22, 155201–155210 (2011).CrossRefGoogle ScholarPubMed
Kung, S., “VLSI array processors.” ASSP Magazine, IEEE, 2(3), 4–22 (1985).CrossRefGoogle Scholar
Sharad, M., Augustine, C. et al., “Boolean and non-Boolean computation with spin devices.” In Electron Devices Meeting, 2012 IEEE International, (2012).

Save book to Kindle

To save this book to your Kindle, first ensure [email protected] is added to your Approved Personal Document E-mail List under your Personal Document Settings on the Manage Your Content and Devices page of your Amazon account. Then enter the ‘name’ part of your Kindle email address below. Find out more about saving to your Kindle.

Note you can select to save to either the @free.kindle.com or @kindle.com variations. ‘@free.kindle.com’ emails are free but can only be saved to your device when it is connected to wi-fi. ‘@kindle.com’ emails can be delivered even when you are not connected to wi-fi, but note that service fees apply.

Find out more about the Kindle Personal Document Service.

Available formats
×

Save book to Dropbox

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Dropbox.

Available formats
×

Save book to Google Drive

To save content items to your account, please confirm that you agree to abide by our usage policies. If this is the first time you use this feature, you will be asked to authorise Cambridge Core to connect with your account. Find out more about saving content to Google Drive.

Available formats
×