Book contents
- Frontmatter
- Contents
- Figures
- Tables
- Foreword
- Acknowledgments
- 1 Introduction
- 2 Projection-based model order reduction algorithms
- 3 Truncated balanced realization methods for MOR
- 4 Passive balanced truncation of linear systems in descriptor form
- 5 Passive hierarchical model order reduction
- 6 Terminal reduction of linear dynamic circuits
- 7 Vector-potential equivalent circuit for inductance modeling
- 8 Structure-preserving model order reduction
- 9 Block structure-preserving reduction for RLCK circuits
- 10 Model optimization and passivity enforcement
- 11 General multi-port circuit realization
- 12 Reduction for multi-terminal interconnect circuits
- 13 Passive modeling by signal waveform shaping
- References
- Index
7 - Vector-potential equivalent circuit for inductance modeling
Published online by Cambridge University Press: 19 January 2010
- Frontmatter
- Contents
- Figures
- Tables
- Foreword
- Acknowledgments
- 1 Introduction
- 2 Projection-based model order reduction algorithms
- 3 Truncated balanced realization methods for MOR
- 4 Passive balanced truncation of linear systems in descriptor form
- 5 Passive hierarchical model order reduction
- 6 Terminal reduction of linear dynamic circuits
- 7 Vector-potential equivalent circuit for inductance modeling
- 8 Structure-preserving model order reduction
- 9 Block structure-preserving reduction for RLCK circuits
- 10 Model optimization and passivity enforcement
- 11 General multi-port circuit realization
- 12 Reduction for multi-terminal interconnect circuits
- 13 Passive modeling by signal waveform shaping
- References
- Index
Summary
As VLSI technology advances with decreasing feature size as well as increasing operating frequency, inductive effects of on-chip interconnects become increasingly significant in terms of delay variations, degradation of signal integrity, and aggravation of signal crosstalk [72, 116]. Since inductance is defined with respect to the closed current loop, the loop-inductance extraction needs to specify simultaneously both the signal-net current and its returned current. To avoid the difficulty of determining the path of the returned current, the partial element equivalent circuit (PEEC) model [101] can be used, where each conductor forms a virtual loop with infinity and the partial inductance is extracted.
To model inductive interconnects accurately in the high frequency region, RLCM (M here stands for mutual inductance) networks under the PEEC formulation are generated from discretized conductors by volume decomposition according to the skin-depth and longitudinal segmentation according to the wavelength at the maximum operating frequency. The extraction based on this approach [59, 83, 84] has high accuracy but typically results in a huge RLCM network with densely coupled partial inductance matrix L. A dense inductively coupled network sacrifices the sparsity of the circuit matrix and slows down the circuit simulation or makes the simulation infeasible. Because the primary complexity is a result of the dense inductive coupling, efficient yet accurate inductance sparsification becomes a need for extraction and simulation of inductive interconnects in the high-speed circuit design.
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- Information
- Advanced Model Order Reduction Techniques in VLSI Design , pp. 118 - 136Publisher: Cambridge University PressPrint publication year: 2007