1. Introduction

Electronic devices based on GaN have attracted growing attention during the past years. This is mainly due to the promising material properties of GaN with respect to performance improvements for high-frequency power modules. To date, remarkable AlGaN/GaN FET-device results have been published with f_max≈140 GHz for small signals Reference Chu, Green and Eastman[1] and 6.9 W/mm output power density at 10 GHz Reference Sheppard, Doverspike, Pribble, Allen, Palmour, Kehias and Jenkins[2]. To further increase the performance and provide reliable operation it is important to investigate possible limiting factors. In this report, we discuss a drain current delay effect and its removal by either a UV-illumination or by applying a high V_DSto the device in the on-state.

2. Device fabrication

The epitaxial layer structure of the the FETs was grown in a vertical MOCVD reactor at 1100°C. A 100 nm AlN nucleation layer, a 3 μm GaN buffer and a 23 nm Al_0.3GaN top layer were deposited on a (0001) n⁺-SiC substrate. No dopants were used. The undoped GaN buffer was deposited at a growth rate of 2 μm/h and a V/III ratio of about 4000. These growth conditions resulted in a smooth surface morphology. Undoped layers grown under these conditions are typically highly resistive (n<5·10¹⁵/cm³) which is indispensable for achieving good pinch-off behaviour of electronic devices.

Mesa isolation was achieved by RIE dry etching with a photoresist mask. The ohmic metallisation consisted of a Ti/Al/Ni/Au layer structure. Pt/Au was evaporated for the gate contacts.

Hall measurements at RT yield mobilities of μ=1900 cm²/Vs and sheet carrier concentrations of n_s=3.5·10¹²/cm². For a fully strained AlGaN layer with an Al mole fraction of 30%, a piezoelectrically induced sheet charge of above 10¹³/cm² is expected Reference Ambacher, Smart, Shealy, Weimann, Chu, Murphy, Schaff, Eastman, Dimitrov, Wittmer, Stutzmann, Rieger and Hilsenbeck[3]. The discrepancy between the measured and the expected carrier concentration may arise from relaxation of the Al_0.3GaN layer or from trapping effects. The ohmic contact resistance R_c varies between 0.6 and 0.9 Ωmm after alloying at 900°C in N₂ ambient.

3. Results and discussion

At a gate-length of 1 μm, the FETs yield a saturation current of 450 mA/mm and a maximum transconductance of 200 mS/mm measured with a HP4145 parameter analyzer. Good ohmic contacts and the high electron mobility provide a low knee voltage of 3 V. The ratio I _D (on>I _D (off) is larger than 10⁶ due to extremely low gate-leakage currents. In a two terminal setup, gate-drain breakdown occurs at 110 V and is independent of the gate-drain spacing from 1.4 to 6 μm. The mesa isolation is about 40 GΩ measured at 30 V between two different mesas. As the etch depth is only 100 nm, this result indicates that the buffer is highly resistive.

Figure 1 shows the output characteristic of a 20 μm device. The FET sustains its maximum drain current of 540 mA/mm up to V_DS=49 V (Figure 1). The corresponding power dissipation of 26.5 W/mm did not destroy the device due to the excellent thermal conductivity of the SiC substrate. This measurement was carried out under UV-illumination with a Hg-lamp. In order to obtain a well defined state of the device these conditions were chosen since the device performance is dependent on the previous biasing conditions, as discussed below.

Figure 1. Output characteristic measured under UV-illumination.

Measuring the output characteristic of the FETs under room light, a drastic current reduction is observed when the device is measured for a second time, 10 s after the first measurement. Figure 2 shows the topmost traces of the output characteristics measured for the first time (device was at equilibrium), 10 seconds later and a third time after a brief UV-illumination. Obviously, the current reduction can be removed by incident photons. This current reduction can equally be removed by applying a drain voltage V_DS>25 V. Before measuring this trace, the device was pinched off at V_GS ⁰=−10 V for 5 min to get a pronounced current reduction (dotted line). The sudden removal of the current reduction at V_DS>25 V can be explained by field enhanced carrier emission from traps. At V_DS=25 V the electrical field between drain and gate is at least 20 MV/m.

Figure 2. Topmost trace of the output characteristic for V_GS=1V: a) after several hours at roomlight and zero bias (straight line), b) 10s afterwards (dashed line), c) after brief UV-illumination (dash-dotted line). The dotted line shows the topmost trace after pinching off the device for 5 min.

It is observed that the current reduction is influenced by the “history” of the gate voltage. Hence, the transients of the drain current I_D at fixed drain and gate biases were studied for different gate pre-biasing conditions. This pre-biasing is denoted by the superscript ⁰. Figure 3 shows the results of I_D(t). Before t=0, the device was pre-biased for 5 min at the V_GS ⁰ value indicated in the figure and at V_DS ⁰=100 mV. At t=0, the device was turned on (V_GS=0 V) and I_D was recorded for 20 000 s. A low V_DS value was applied in order not to influence the current recovery process by the applied drain voltage. As the drain current is very sensitive to incident light, the whole measurement was carried out in the dark and prior to each measurement the device was kept for 5 hours at zero bias in the dark to achieve approximately thermodynamic equilibrium. The current reduction effect becomes more pronounced as a lower pre-biasing value V_GS ⁰ is chosen.

Figure 3. The first 400s of the drain current transients for V_GS=0V and V_DS=100 mV measured for 5 hours in the dark. Before each transient the sample was biased at V_DS ⁰=100 mV and the V⁰ _GS indicated in the figure.

After V_GS ⁰=−10 V it takes the drain current several seconds to reach even 1% of its saturation value. At such a heavy pre-biasing, I_D(t) has a point of inflection indicating a second order effect. No point of infliction is observed for V_GS ⁰≥−5 V. The transients can be divided into two regions: A region of fast current increase (0≤t≤1000 s) and a region of slow current increase (t>1000 s). These results may be explained assuming that traps are responsible for the current reduction. However, the location of the traps cannot be identified from these experiments. Charged deep levels in the region below the gate may deplete the channel of mobile carriers. Also, under large negative gate bias, the lateral field between gate and drain may lead to a charge redistribution on the surface or in the AlGaN barrier layer.

Assuming the existence of traps in the semiconductor or on the surface, the following simple approach can be pursued to explain the observed current reduction: If the traps can be negatively charged, this immobile charge depletes the channel and limits the drain current. As a result, after turning on the device, the channel remains highly resistive. Subsequently, the system relaxes slowly towards its equilibrium state by emission of the trapped electrons and the drain current builds up. Invoking the principle of detailed balance and neglecting hole emission from the traps, the time constant τ of the build-up process should follow the relationship Reference Schroder[4]:

is the thermal velocity of electrons, σ the electron capture cross section, k the Boltzmann constant, N_c the effective density of states in the conduction band, τ the time constant and E_a the activation energy. In this model, the transients show an exponential behaviour:

This simple model cannot describe the transients as a whole, but for the region of fast current increase it seems to be at least a valid approximation.

Using this approach, the transients measured at different temperatures (RT—280°C, Figure 4) were fitted with (Equation (2)) and the time constant τ was extracted. From the temperature dependence of τ an activation energy E_a=280 meV and a capture cross section of 4.4·10⁻¹⁸cm² are extracted from the Arrhenius-plot as depicted in Figure 5.

Figure 4. Drain-current transients measured at different temperatures with V_GS=1 V and V_DS=6 V. Prior to the measurement the device was pre-biased at V_GS ⁰=−10 V and V_DS ⁰=6 V for 5 min.

Figure 5. Arrhenius-plot of the time constants τ determined from the drain current transients measured at different temperatures.

To investigate the region of slow drain current increase we studied the wavelength dependence of the steady state drain current I_D ^∞. The device was biased at V_GS=0 V and V_DS=100 mV for one day in the dark before I_d ^∞(dark) was measured. In the following the device was illuminated with a light intensity of 0.4 W/m² with the wavelengths λ= 1500 nm, 1200 nm and the values indicated in Figure 6. The corresponding drain current was measured after 10,000 s of constant illumination. For the long wavelengths we used a halogen lamp and a monochromator for wavelength selection. A Xe-lamp was used for the short wavelengths. At λ=1500 nm and 1200 nm no significant current variation was observed. For λ≤900 nm I_D increased. The energy of the onset of the current increase is well below the bandgap energy of GaN. The results indicate, that the material exhibits pronounced persistent photoconductivity (PPC).

Figure 6. Steady state drain-currents for V_DS=100 mV and V_GS=0 V. The light intensity is 0.4 W/m².

4. Conclusion

It was shown that the drain current in the investigated undoped AlGaN/GaN FETs is dependent on the gate and drain bias history. The drain current recovery is a function of temperature with an activation energy of E_a=280 meV. The physical origin of the current reduction after pinch-off and its relation to the PPC is not yet understood. Further work has to be done to determine if the extracted activation energy E_a is related to a discrete state or an emission barrier Reference Polyakov, Smirnov, Govorkov, Shin, Skowronski and Greve[5] Reference Hirsch, Wolk, Walukiewicz and Haller[6] Reference Chen, Chen, Lee and Feng[7] Reference Qiu and Pankove[8]. The assumption that the PPC and the current reduction are of the same origin is under current investigation. The effect of the current reduction needs to be identified and eliminated as it may be detrimental to the large signal performance of RF power devices.