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An accurate SPICE-compatible circuit model for power FLYMOSFETs

Published online by Cambridge University Press:  08 August 2007

A. Galadi*
Affiliation:
LAAS-CNRS, 7 Av. du Colonel Roche, 31077 Toulouse Cedex 4, France Université Cadi Ayyad, Marrakech, Morocco
F. Morancho
Affiliation:
LAAS-CNRS, 7 Av. du Colonel Roche, 31077 Toulouse Cedex 4, France
K. Benhida
Affiliation:
Université Cadi Ayyad, Marrakech, Morocco
M. M. Hassani
Affiliation:
Université Cadi Ayyad, Marrakech, Morocco
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Abstract

In this paper, a new SPICE-compatible circuit model for low voltage, low on-resistance power FLYMOSFETs is presented for the first time. In this new structure, the improvement of the on-resistance has been obtained by inserting floating islands in the lowly doped layer. Our modelling is based on device physics, analytical study and on experimental characterization. The inter-electrode capacitances are modelled accurately as nonlinear functions, and good agreement between simulation and measurements is found.

Keywords

Type
Research Article
Copyright
© EDP Sciences, 2007

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References

B.J. Baliga, Modern power devices (J. Willey & Sons, 1992)
N. Cézac, F. Morancho, P. Rossel, H. Tranduc, A. Peyre-Lavigne, A new generation of power unipolar devices: the concept of the FLoating Islands MOS Transistor (FLIMOST), Proceedings ISPSD'2000, Toulouse, 69
Chen, X.B., Wang, X., Sin, J.K.O., IEEE Trans. Electron Devices 47, 1280 (2000) CrossRef
W. Saitoh, I. Omura, K. Tokano, T. Ogura, H. Ohashi, Ultra low On-resistance SBD with P-buried floating layer, Proc. ISPSD'02, Santa Fe, p. 33 2002
Fujihira, T., Jpn J. Appl. Phys. 36, 6254 (1997) CrossRef
F. Di Giovanni, G. Bazzano, A. Grimaldi, A New PSPICE Power MOSFET Subcircuit with Associated Thermal Model, PCIM'2002 Europe, 271 (2002)
G. Verneau, L. Aubard, J.-C. Crébier, C. Schaeffer, J.-L. Schanen, Empirical Power MOSFET Modeling: Practical Characterization and Simulation Implantation, 37th IAS (Industry Applications Conference) Annual Meeting (2002), 2425
K. Shenai, C. Cavallaro, S. Musumeci, R. Pagano, A. Raciti, Modeling low-voltage power MOSFETs as synchronous rectifiers in buck converter applications, 38th IAS (Industry Applications Conference) Annual Meeting (2003), 1794
Buttay, C., Morel, H., Allard, B., Lefranc, P., Brevet, O., IEEE Trans. Power Electron. 21, 613 (2006) CrossRef
ATLAS II, 2D Device Simulation Framework, User Manuel, Silvaco International (2000)
M. Gharbi, La tenue en tension et le calibre en courant du transistor MOS vertical dans la gamme des moyennes tensions, Thèse, Université Paul Sabatier, Toulouse (1985)
Rossel, P., Guégan, G., Martinot, H., Rev. Phys. Appl. 14, 763 (1979) CrossRef
Shenai, K., Electron. Lett. 27, 280 (1991) CrossRef