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Physical and technological limitations of NanoCMOS devicesto the end of the roadmap and beyond

Published online by Cambridge University Press:  10 January 2007

S. Deleonibus
S. Deleonibus*
Affiliation:
CEA-LETI/NANOTEC, CEA-Grenoble, 17 rue des Martyrs, 38054 Grenoble Cedex 09, France
*
[email protected]
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Abstract

Since the end of the last millenium, the microelectronics industry has been facing new issues as far as CMOS devices scaling is concerned. Linear scaling will be possible in the future if new materials are introduced in CMOS device structures or if new device architectures are implemented. Innovations in the electronics history have been possible because of the strong association between devices and materials research. The demand for low voltage, low power and high performance are the great challenges for the engineering of sub 50 nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power consumption are reviewed. The issues in the field of gate stack, channel, substrate, as well as source and drain engineering are addressed. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. By introducing new materials (Ge, diamond/graphite carbon, HiK, ...), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating also new disruptive devices. For example, the association of C-diamond with HiK, as a combination for new functionalized Buried Insulators, will bring new ways of improving short channel effects and suppress self-heating. Because of the low parasitics required to obtain high performance circuits, alternative devices will hardly compete against logic CMOS.

Keywords

Type
Review Article
Information
The European Physical Journal - Applied Physics , Volume 36 , Issue 3 , December 2006 , pp. 197 - 214
Copyright
© EDP Sciences, 2006

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