Dislocations present at GaAs/Si interfaces have been characterized using transmission electron microscopy in plan-view. The GaAs was grown by molecular-beam epitaxy on Si (001) substrate tilted* towards the [110] direction. The dislocation network at the interface consists primarily of orthogonal edge dislocations with Burgers vectors of a/2[110] and a/2[110]. However, displacements of these dislocation lines at the interface are observed. These displacements can be attributed to the interaction of 60* dislocations with the network of orthogonal edge dislocations. The density of these 60* dislocations along [110] direction is different from that along [110] direction.

Heteroepitaxial growth of CaF2 films on (511)Si and GaAs films on CaF2/Si(511) structures is investigated. CaF2 films and GaAs films are grown by vacuum evaporation and molecular beam epitaxy, respectively. Ion channeling measurements and replica transmission electron microscopy show that CaF2 films having good crystalline quality and surface steps can be formed by annealing at 900°C for 30 sec after the growth at 550° C. GaAs films having smooth surfaces and good crystalline quality can be grown on the annealed CaF2/Si(511) structures.

Epitaxial growth using thermal annealing and a strained layer superlattice is studied to obtain high-quality GaAs device layers on Si substrates. Crystalline quality of GaAs-on-Si is found to improve with thermal cyclic annealing at temperatures higher than the growth temperature and cooling down to 300°C. It is also found that the optimum InGaAs/GaAs strained layer superlattice buffer structure is one whose total thickness is several times the calculated critical thickness for the average In-mole fraction of the SLS buffer. Configurations and structures of dislocation reductions are ex-amined by TEM observations. A GaAs solar cell is successfully constructed and is found to show total area efficiencies of 18.3% under AM 0 and 20.0% under AM 1.5 conditions.

Low temperature cleaning process of Si surface and the subsequent epitaxial growth of GaAs on Si by Plasma-Assisted Epitaxy in hydrogen plasma are described. As the rf power applied to excite the plasma is increased, the temperature for both cleaning and epitaxial growth processes can be reduced. Then GaAs epitaxial layers were directly grown on Si at 440°C.

In this paper, we demonstrate the growth of heteroepitaxial thin films of GaAs at low temperatures on Si(100) and Ge(100) substrates by direct deposition from controlled, low-energy (30-50 eV), mass-separated beams of 69Ga+ and 75As+ ions. This represents the first use of two fully ionized beams for the growth of compound semiconductor thin films. Mixing of the constituents was accomplished by periodically switching tile analyzing magnet to alternate between deposition of Ga and As at approximately monolayer intervals. Ion channeling and transmission electron microscopy show that GaAs films grown on Ge substrates at 400°C are free of the microtwins and stacking fault defects which emanate from the interface of GaAs similarly grown on Si. Single-crystal GaAs films with ion channeling minimum yields of around 6% have been grown on Ge(100) substrates at temperatures from 520°C down to as low as 320°C.

Two problems facing MOCVD grown GaAs-on-Si are firstly, scale up to 3” and greater wafer diameter with acceptably uniform layer thicknesses and electrical and optical properties, and secondly the achievement of adequate device isolation through the use of buffer layers of low doping density (≤1014 cm−3). We have investigated the thickness uniformity and 300K photoluminescence intensity of 3” Ø, MOCVD grown GaAs layers on Si substrates by whole wafer mapping of these parameters, and correlate the variations found with the gas flow direction during deposition of the GaAs. We have overcome the high background doping densities (n =5−20 × 1015 cm2) in the material by a buried Be implant (1−5 × 1012 at 120 keV) followed by 850°C, 3 sec annealing. This provides adequate isolation for MESFETS and we fabricated such devices with gm's of 160-175 mS mm−1 using our standard process. These values are similar to homoepitaxial MESFETS fabricated in the same way.

The MOCVD-grown layers of GaAs/Si(001), InP/GaAs/Si(001), and ZnS/Si(111) were studied using X-ray rocking curve (XRC), double crystal topography (DCT), and Nomarski phase contrast microscopy. The layer qualities of GaAs/Si, InP/GaAs, and InP/GaAs/Si from the XRC full width at half maximum (FWHM) agreed well with these determined from the Nomarski phase contrast microscopy. The in-plane lattice mismatch (parallel X-ray strain) was 3.71% for GaAs/Si. In the double heteroepitaxial layer (InP/GaAs/Si), the parallel X-ray strain of GaAs was 4.03% with respect to Si. The parallel X-ray strain was larger than the perpendicular X-ray strain in GaAs/Si, perhaps due to the mismatch in thermal expansion coefficients between GaAs and Si. Dislocation densities estimated from the rocking curve linewidth were 5.30 × 107 cm−2 for GaAs/Si, 3.27 × 108 cm−2 for InP/GaAs. We also present the double crystal X-ray topographs of the III-V/Si and II-VI/Si samples.

New low-temperature cleaning and growth processes are presented using hydrogen plasma. Cleaning of GaAs and Si surfaces are possible above 200°C and 300°C, respectively. Single-domain GaAs thin films are successfully grown on Si at 400°C using metal-organic compounds for both Ga and As. Selective growth of GaAs is demonstrated at 400°C on a Si surface partially covered withSiO2.

The relatively high background carrier concentration obtained in unintentionally doped epitaxial layers of III-V materials imposes a limitation on applications of the hydride VPE process. It is usually attributed to impurities in the gas sources. Results are presented for InGaAs grown by hydride VPE using a range of growth conditions. Carrier concentrations and growth rates for the various samples were determined using, respectively, Polaron electrochemical profiler measurements and scanning electron microscopy. It is shown that the observed background carrier concentration increased with increasing input mole fraction of arsine under conditions of constant growth rate. This strongly implicates the arsine feed gas as a predominant source of impurity. Attempts to purify the arsine feed gas using sodium alumina-silicate molecular sieves are described. Polaron electrochemical profiler measurements and Hall effect measurements on samples grown both with and without molecular sieves in the arsine feed line are presented. From a comparison of the corresponding values of carrier concentration and mobility it is shown that Type 4A molecular sieves were not effective in removing dopant impurities from the 4% arsine-hydrogen mixture used.

We have implanted most dopant elements into GaAs, GaP, InP, and InSb, to energies from 10 to 700 keV, and a few up to 2.4 MeV, in random and channeled orientation, annealed some of these implants, and measured the depth distributions using secondary ion mass spectrometry (SIMS) . We have calculated values of Rm, Rp, ΔRp, γ1, β2, using an LSS formulation, and measured these same profile parameters for the experimental profiles using a Pearson IV computer fitting routine. We describe a study of the fabrication of self-aligned W-gate FETs in GaAs using Si-implanted channels and source/drains, and a buried p implant (Be or Mg) to compensate the backside (tail) of the Si profile. The implant profiles and electrical device characteristics, including the effects on AVt of various implant conditions, are discussed.

Elevated temperature ion bombardment of GaAs has been examined to investigate the nature of residual damage and the interplay between bombardment-induced defect production and dynamic annealing. The nature of disorder is found to depend strongly on ion energy, species, dose, dose rate and substrate temperature. A temperature regime is identified in which dynamic annealing leads both to the efficient formation of band gap traps for carrier removal and to the low temperature crystallization of pre-existing amorphous layers.

The implantation of Ar+ ions into AlAs/GaAs layered samples is shown to give very different damage structures in the two materials. While the GaAs is relatively easily amorphised, the AlAs is quite resistant to damage accumulation and remains crystalline for the ion doses employed in these investigations. The behaviour of the different damage structures when subjected to rapid thermal annealing treatments is described in some detail. It is demonstrated that differences in the initial damage state have a strong influence upon the nature of lattice defects produced by annealing.

MeV oxygen ion implantation in GaAs/AlGaAs has been shown to provide a simple and very promising technique for quantum well laser fabrication. A l0μm stripe single quantum well (SQW) graded-index separation confinement heterostructure (GRINSCH) laser made in this way has achieved high performance with high quantum differential efficiency, low threshold current and good electrical isolation characteristics. MeV oxygen ion implantation with optimum thermal annealing produces a deep buried electrical isolation layer in n-type GaAs and reduces optical absorption in GaAs/AlGaAs quantum well structures. Ion implantation stimulated compositional disordering as well as implanted oxygen-related deep level traps may be considered as important effects for electrical and optical modification of interfaces in GaAs and AIGaAs.

In this article we will illustrate how by suitable furnace design, the radial thermal gradients generated on a GaAs substrate during the post-implant annealing cycle can be virtually eliminated, and how such a technique can result in appreciable improvement in on-wafer activation uniformity (standard deviation better than ± 2%), with virtually constant activation efficiency in going from seed to tail end wafer of a given ingot.

We have investigated the relationship between electrical activation and residual defects in GaAs implanted with 1 MeV Si ions to a fluence of 3×1015 cm−2 and subsequently annealed, using rapid thermal annealing (RTA) for 10 seconds, at temperatures up to 1050°C. Hall measurements show n-type activation that increases in magnitude with increasing annealing temperature to reach a sheet carrier concentration of 2.6×1014 cm−2 after RTA at 1050°C. Two main types of extended defects, perfect and partial dislocation loops, had previously been identified in the as-implanted samples. In addition, a large number of discrete point defect complexes are certainly created but escape detection. We show here a correlation between the annealing of the defects and the recovery of the electrical transport properties. Most of the point defects anneal out between room temperature and 700°C, and it is in this temperature regime that the transport properties show their most significant improvement. For annealing temperatures between 700°C and 1050°C, the mobility of the carriers decreases slightly while the carrier concentration gradually approaches saturation. Concurrently, the loops grow in size while decreasing in number and eventually anneal out. However, after annealing at 1050°C, while most of the extended defects have disappeared, only about 9% of the implanted atoms had been activated, suggesting that residual point defect centers control the activation of Si dopants in MeV implanted GaAs.

Maintaining As overpressure during capless post-implantation annealing through the use of the face-to-face proximity configuration has proved to be a reproducible technique with less process parameters to control than the alternative techniques of capped or arsine annealing. An investigation of carrier mobility and dopant activation as a function of annealing temperature resulted in an optimum annealing temperature of 840 °C with activation improving for 9 min heat-up time as compared to a 14 min heat-up time. An increase in activation with anneal time during isothermal annealing was also observed. Dopant redistribution during annealing was modeled with an experimentally derived diffusion coefficient of 2×10−14 cm2/sec. This value is close to the diffusion coefficient published for capped annealing. Dopant redistribution in the near-surface (1000 Å) region was verified using SIMS. Based on presently available data there is no evidence for similar dopant redistribution during capless arsine annealing and this redistribution probably occurs whenever excess vacancy generation/redistribution is taking place, as during capped annealing and during proximity annealing.

We describe the effects of rapid thermal annealing on the photoluminescence (PL) and electrical properties of heteroepitaxial ZnSe grown by molecular beam epitaxy on GaAs, using either no cap or plasma-deposited SiO2, Si3N4, or diamond-like C caps, and annealing temperatures from 500 to 800°C. Capless anneals (in contact with GaAs) produce badly degraded PL properties, while capped anneals can prevent this degradation. We show that Si3N4 is significantly more effective in preventing Zn out-diffusion through t e cap than previously employed SiO2 films, as evidenced by less pronounced PL features related to the creation of Zn vacancies during the anneal. Implant damage tends to enhance the Zn vacancy formation. Rapid thermal annealing with Si3N4 caps is shown to optically activate shallow N acceptor implants.

A thermal analysis is performed to simulate the rapid heating process for ion implanted GaAs with consideration of the doping effect. The results are for cases with various concentrations and thicknesses of doping layer. Also studied are the heating processes for silicon dioxide capped GaAs. The effects of the thickness of the oxide layer are discussed. The magnitude of the temperature differences across the wafer is addressed. The present analysis considers xenon-arc lamps and tungsten-halogen lamps as the light sources.

We have constructed a multiple wafer arsine ambient rapid thermal anneal (RTA) system and have applied it to the fabrication of high-performance refractory-gate self-aligned GaAs MESFETs. This has allowed us to take advantage of some of the features of rapid thermal annealing for these devices (reduced dopant movement and gate-channel interaction) without the difficulties of capped RTA (decapping problems, cap thermal mismatch stress driven dopant movement and gate-channel interaction) or the uncertain As loss characteristics of uncapped or proximity RTA. The anneal system uses a cylindrical furnace with a graphite boat heated by tungsten lamps with a 60 KW maximum power input. This allows heating rates in excess of 100°C/sec for up to four, two-inch wafers per run with a controlled arsine ambient of 0–20 Torr in an inert gas carrier. Closed loop temperature control is accomplished using a 5 μm wavelength optical pyrometer. The system has been designed to collect the As cracked from AsH, in a downstream trap and essentially no As is deposited in the wafer load area.

Using arsine ambient RTA to anneal 15 KV 20Si+ self-aligning implants for GaAs MESFETs with MOCVD grown channels (30 nm, 1.7 × 1018/cm3), we have been able to fabricate enhancementmode self-aligned MESFETs with gm/gd > 20 and extrinsic k-factor as large as 765 mS/V-mm for 0.15 μm gate length.

For compound semiconductors with the diamond structure, (111) planar channel walls contain different atomic species when viewed from different sides; thus under channeling conditions, the yields of ions backscattered from the different species oscillate with depth in opposite senses for ion beams directed towards the different channel sides. We have studied this effect for 2 MeV He ions in a (111) channel of InP crystals. The application of this channeling phenomenon to the determination of the lattice sites of solute atoms was demonstrated for implanted In and Sb atoms at different depths in GaP.