We report an unusual circuit failure mode induced by short-lived extrusions observed during DC and AC electromigration (EM) tests of quarter-micron damascene copper interconnects. This novel “soft” failure mode consists of extrusions forming, then self-dissolving before the traditional permanent void or extrusion failure. These failures shorten the lifetime significantly and bring new challenges to reliability tests. Two self-dissolution mechanisms under DC test conditions are discussed and extrusion shape evolution is modeled assuming both capillary and electron wind forces are present. Our model confirms that the electrical stress will accelerate the shape evolution process.

Au/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

Electromigration tests were performed on passivated electroplated Au four terminal Kelvin line structures using the conventional in situ resistance monitoring technique. The stress conditions were a current density of 2.0 MA/cm2 with ambient temperatures ranging from 325°C to 375°C. The temperature coefficients of resistance (TCR) values were measured prior to current stressing to calculate the Joule heated film temperatures. The times to failure (lifetimes) for the Au line structures were considered as a 50% ΔR/R0 change. The median time to failure (t50%) was plotted against the inverse film temperature to determine the activation energy value as 0.59 ± 0.09 eV. Failure analysis of void location and suggested diffusion mechanism will be discussed.

Electrostatic force microscopy (EFM) was used to measure the extent of dielectric damage from plasma processing of nanoporous, low k methyl silsesqioxane (MSQ) interconnect structures with approximately 50 nm spatial resolution. Single level patterns were formed in 200 nm thick MSQ films by reactive ion etching (RIE) and were subsequently backfilled with an MSQ layer that was not exposed to plasma to act as a reference. The backfill was performed on as-etched structures with the photoresist intact and on structures in which the photoresist was removed by an oxygen plasma (ash) treatment. The EFM images on cross sections and feather sections show that the damage from the RIE penetrated ∼100 nm in from the sidewall and that the redeposited polymer had a higher k than the MSQ (k∼2.2). The etched and ashed MSQ exhibits a higher dielectric constant than the reference MSQ if it was exposed to water and has nearly the same dielectric constant as the reference with no water exposure. This suggests that the damage from the ash acts to make the MSQ hydrophilic.

Reducing interline capacitance and line resistance is required to minimize RC delays, reduce power consumption and crosstalk below 100nm node technology. For this purpose, various inorganic- and organic polymers have been tested to reduce dielectric constants in parallel with the use of copper as metal line. Lowering the dielectric constants, in particular, causes the detrimental effect on mechanical properties, and then leads to film damage and/or delamination during chemical-mechanical planarization CMP) or repeated thermal cure cycles. To overcome this issue, new carbon-bridged hybrid materials synthesized by organometallic silane precursors and sol-gel reaction are proposed.

In this work, we have developed new organic-inorganic hybrid low-k dielectrics with linear or cyclic carbon bridged structures. The differently bridged carbon structures were formed by a controlled reaction. 1H NMR, 29Si NMR analysis and GC/MSD analysis were conducted for the structural characterization of new hybrid low-k dielectric. The mechanical and dielectric properties of these hybrid materials were characterized by using nanoindentation with continuous stiffness measurement and Al dot MIS techniques. The results indicated that these organic-inorganic hybrid materials were very promising polymers for low-k dielectrics that had low dielectric constants with high thermal and mechanical properties. It has been also demonstrated that electrical and mechanical properties of the hybrid films could be tailored by copolymerization with PMSSQ and through the introduction of porogen.

The constant push for decreasing the Resistance-Capacitance (RC) delay has led to the implementation of Multilevel Metallization (MLM) scheme for interconnect wiring, Cu as the wiring material and low ê materials as Interlayer Dielectric (ILD). Polymeric materials are being explored to replace SiO2 based ILD materials in the next generation ICs. Several reliability and integration challenges arise during integration of the candidate polymeric ILD when they are subjected to planarization by Chemical Mechanical Polishing (CMP). In this research, we have performed a comparative study of certain candidate low ê materials: 1) undoped SiO2 (standard), 2) Polyimide and 3) Benzocyclobutene (BCB). We have studied the impact of reduction in dielectric constant on the mechanical and tribological properties, and the CMP performance of these ILD materials. The adverse effect of shear and mechanical abrasion due to decreased mechanical properties of the low ê materials induced numerous defects during CMP.

A new testing technique for the characterization of the mechanical behavior of the interconnect structures of integrated circuit devices is introduced in this paper. Modified crosssectional nanoindentation (MCSN) is the result of extending cross-sectional indentation (CSN) to patterned structures. As in conventional CSN, a Berkovich indenter is used to initiate fracture in the silicon substrate beneath the interconnect structure. The cracks propagate through this structure, preferentially along the weakest interfaces in the system. A FIB (Focused Ion Beam) is used for sample preparation, machining a trench parallel to the indentation surface. In this way, the crack growth can be better controlled and the problem may be modeled in two dimensions.

The technique has been used to study crack propagation in patterned structures as a function of thin film composition and processing. The results obtained, in terms of crack length along each interface studied, correlate well with the fracture energy measured by four-point bending (4 PB) in blanket films of the same materials. Finite element modeling of the stress fields in the vicinity of the crack tip has been carried out to understand the crack paths observed.

A porous ultra low k PECVD dielectric has been evaluated at SEMATECH for 45 nm and beyond technology node applications. Material structure, integration performance, and electrical characteristics were investigated in a one level metal single damascene integrated structure.

The fracture and fatigue properties of LIGA nickel MEMS structures were evaluated by microtensile and fatigue test methods. A microtensile/fatigue device was developed and specimens with feature size ten micrometers were used. The fatigue property was derived from displacement amplitude – the number of cycles to failure curve by applying a dynamic load with a piezoelectric actuator. The tensile/fracture properties after various cyclic loading were also measured. Both fatigue and tensile test results showed a cyclic softening phenomenon.

Mesoporous low dielectric poly(silsesquioxane) thin films have been fabricated by templating various surfactants such as cetyltrimethyl ammonium bromide (CTAB) or 4-octylphenol polyethoxylate (OPE) in the silsesquioxane polymer matrix and their properties of the thin films characterized by electrical, mechanical and structural characterization. Depending on the types of the surfactants, mesoporous poly(silsesquioxane) thin films with different porosities have been formed. The dielectric constant (k) of the films depended on the content or porosity of the surfactants. The dielectric constants of ca. 2.2–2.4 were obtained for the films with relative porosities of about 15–30 vol. % to the polymer matrix itself. The elastic modulus of the films showed a dependency on the type, content of the surfactants and was ca. 2.9 GPa with the k value of ca. 2.38.

We demonstrate the evolution of microstructure and deformation associated with the use of electrical methods for evaluating mechanical reliability of patterned interconnects on rigid substrates. Thermomechanical fatigue in aluminum and copper interconnects was induced by means of low frequency (100 Hz), high density (> 10 MA/cm2) alternating currents, which caused cyclic Joule heating and associated thermal expansion strains between the metal lines and oxidized silicon substrate. The failure mechanism involved formation of localized plasticity, which caused topography changes on the free surfaces of the metal, leading to open circuit eventually taking place by melting at a region of severely reduced cross-sectional area. Both aluminum and copper responded to power cycling by deforming in a manner highly dependent upon variations in grain size and orientation. Isolated patches of damage appeared early within individual grains or clusters of grains, as determined by a quasi in situ scanning electron microscopy and automated electron backscatter diffraction measurement. With increased cycling, the extent of damage became more severe and widespread. We document some examples of the types of damage that mechanically confined interconnects exhibited when subjected to thousands of thermal cycles, including growth and re-orientation of grains in a systematic manner. We observed in the case of Al-1Si certain grains increasing by nearly an order of magnitude in size, and reorienting by greater than 30°. The suitability of electrical methods for accelerated testing of mechanical reliability is also discussed.

In sub-micron dual damascene Cu interconnects, electromigration occurs mainly along the interfaces between Cu and dielectric cap layer. Many reports have shown that the interface of Cu/dielectric cap is the dominant diffusion path. In-situ electromigration experiments were carried out recently by A. V. Vairagar etal [APPL. PHYS. LETT., 85, 2502 (2004)] to investigate the electromigration failure mechanisms in the upper and lower layers in dualdamascene Cu test structures. It was found that electromigration-induced void first nucleates at locations which are far from the cathode, then moves along the Cu/dielectric cap interface in opposite direction of electron flow, and eventually causes void agglomeration at the via in the cathode end to open the interconnect. In the present study, immersion Sn (20 nm) was employed after CMP and before SiN deposition. All the samples, with a line-width of 0.28 um, were assessed by package level electromigration tests at 300°C under a current density of 3.6MA/cm2. We found that immersion Sn surface treatment effectively introduced the Cu-Sn bonding to the Cu/dielectric interface and has influenced electromigration along the Cu/dielectric interfaces. Failure analysis shows that the samples with these Sn processes have a median-time-to-failure almost 1 order of magnitude larger than the control samples. A careful characterization utilizing FIB and SEM cross-sectional images shows that the failure mechanism has changed due to the Sn surface treatments. After electromigration-induced void nucleation, its movement is blocked by the strong Cu-Sn bonding so that its growth is localized and occurs along grain boundaries. With the increased impedance to surface diffusion, failure analysis seems to indicate that grain boundary diffusion now participates in the void movement and growth, which is proposed to be the reason for the increased lifetime.

The introduction of new dielectrics into silicon chip interconnection technology is necessary to increase electrical performance. Sub-65nm technologies need κ values below 2.5 and the main way to reduce the dielectric constant is to introduce porosity. This work reports results concerning a two steps PECVD porogen approach to perform Ultra Low κ (κ <2.5). The first step is an hybrid material deposition: i.e. an a-SiOC:H matrix containing organic sacrificial inclusions (porogen phase). In the second step, the porogen is removed by a suitable curing to generate porosity. Two siloxane precursors (decamethylcyclopentasiloxane and diethoxymethylsilane) were evaluated as matrix precursors. Their influences, as well as O2 addition in plasma gas feed, in terms of cross-linking and incorporation were evaluated by FTIR analysis. Thermal anneal and UV treatment (thermally assisted) were evaluated as a curing second step. It allows to better understand this critical step which combines porogen removal and material cross-linking. By optimizing deposition and curing parameters, κ value lower than 2.4 were obtained.

An analysis is presented of electromigration-induced migration and oscillatory dynamics of morphologically stable void surfaces based on self-consistent numerical simulations of morphological evolution of voids in metallic thin films. As the morphological stability limit is approached, the migration speed of a stable void deviates substantially from being inversely proportional to the void size, a well-known result that is rigorously valid in an infinite conductor with isotropic material properties. A non-linear shape function that includes both current crowding and diffusional anisotropy effects is used to rescale properly the void migration speed resulting in a universally valid relationship for the migration speed as a function of void size. Furthermore, in grains characterized by high symmetry of surface diffusional anisotropy, our analysis predicts the onset of stable time-periodic states for the void surface morphology that correspond to waves propagating on surfaces of voids that migrate along the metallic film at constant speeds.

Semiconductor industry needs a continuously improvement of integrated circuits performance and an increase of integrated density on silicon. The 2004 ITRS Roadmap underlines the need of dielectric material for ILD with dielectric constant (k) lower than 3 for the 90 nm node and than 2.4 for the 45 nm node. In this work, porous films with k value lower than 2.2 were processed using a porogen approach. Firstly, a material composed of a methylsilsesquioxane (MSQ) matrix and of organic nanoparticles (called porogen) is deposited and baked. Then, this composite is thermally cured to allow the porogens degradation and matrix crosslinking. Different k values were obtained by varying the porogen loading in the composite. Mechanical properties of composite and porous films (before and after porogen removal respectively) were investigated using nanoindentation and FTIR analysis for different porogen loadings (between 0 and 40 %). The composite modulus is higher than the porous film modulus for high porogen loading. This result is interpreted in term of matrix crosslinking. Mechanical properties were also modelized using foam mechanical models. For high porosity level, the best Young modulus fitting is obtained with tetrakaidecaedric cells, which seems in good agreement with porosity morphology.

A systematic investigation of the effect of annealing time and temperature on the incubation period for spontaneous morphology change (SMC) in electrodeposited copper metallization is reported. The incubation time is greatly reduced at higher temperatures. At each temperature, the remaining incubation time at room temperature was found to decrease approximately linearly with increasing annealing time. An Arhennius plot of the measured rates of decrease showed good linearity and yielded a value of 0.48 eV for the activation energy. This is consistent with a vacancy diffusion mechanism for the process occurring during the incubation period and supports our proposed mechanism for SMC.

The growth and size distribution of scallop-type Cu6Sn5 intermetallic compound (IMC) at the interface between molten SnPb solder and Cu was investigated, along with a systematic study of morphology change of Cu6Sn5 morphology change as a function of SnPb solder composition. When SnPb solder composition was changed from eutectic (63Sn37Pb) to about 40Sn60Pb, Cu6Sn5 with round scallop-type morphology was found. In other compositions, the Cu6Sn5 scallops showed faceted scallop-type morphology. This morphological change is due to variation of interfacial energy between Cu6Sn5 and solder with a change of solder composition. The growth rate of Cu6Sn5 layer was proportional to cube root of time, and size distribution was in good agreement with the Flux-Driven-Ripening (FDR) theory. The pre-exponent factor k obtained by the measurement was 2.10×10-14 cm3/sec. Based on the k value, the calculated channel width with was about 2 nm, which was in good agreement with experimental observation by transmission electron microscopy.

The reliability of Cu M1-V1-M2-V2-M3 interconnects with SiN and CoWP cap layers was investigated. Similar to previously reported results, the reliability of CoWP capped structures is much better than identical SiN capped structures. However, it was also observed that the reliability of CoWP capped interconnects was independent of the direction of electrical current flow. This phenomenon is different from what was observed for SiN capped structures, where M2 lines with electron current flow in the upstream configuration (“via-below”) have about three times larger median-time-to-failure than identical lines in the downstream configuration (“viaabove”). This is because the Cu/SiN interface is the preferential void nucleation site and provides the fastest diffusion pathway in such an architecture. Failure analysis has shown that fatal partially-spanned voids usually had formed directly below the via for “via-above” configuration, and fully-spanned voids occurred in the lines above the vias for “via-below” configuration.

On the other hand, failure analysis for CoWP-coated Cu structures showed that partiallyspanned voids below the via do not cause fatal failures in the downstream configuration. This is because the CoWP layer is conducting, and thus able to shunt current around the void. As a result, a large fully-spanning void is required to cause a failure, just like the upstream configuration. Thus the lifetime of an interconnect with a conducting cap layer is independent of whether the current is flowing upstream or downstream.

One of the most common forms of cohesive failure observed in brittle thin films subjected to a tensile residual stress is channel cracking, a fracture mode in which through-film cracks propagate in the film. The crack growth rate depends on intrinsic film properties, residual stress, the presence of reactive species in the environment, and the precise film stack. In this paper, we investigate the effect of various buffer layers sandwiched between a brittle carbon-doped-silicate (CDS) film and a silicon substrate on channel cracking of the CDS film. The results show that channel cracking is enhanced if the buffer layer is more compliant than the silicon substrate. Crack velocity increases with increasing buffer layer thickness and decreasing buffer layer stiffness. This is caused by a reduction of the constraint imposed by the substrate on the film and a commensurate increase in energy release rate. The degree of constraint is characterized experimentally as a function of buffer layer thickness and stiffness, and compared to the results of a simple shear lag model that was proposed previously.

In this paper, we investigated void formation in passivated Cu films focusing on the kinetics of void formation under isothermal annealing as a function of temperature. Interestingly, we found that the kinetics of void formation in Cu films is consistent with that observed in Cu lines, which is driven by the combined effect of thermal stress and mass transport resulting in a peak growth rate at about 250°C. To analyze the observed results, we have calculated the stress state at the <111>/<200> Cu grain boundary to demonstrate the existence of a localized triaxial stress state as a result of elastic anisotropy. To account for void density, x-ray analysis was performed to measure the grain texture using inverse pole figure plot and the result can account for the void density observed. A kinetic model was used to analyze void growth under isothermal annealing. A threshold stress of about 40MPa was deduced for void growth in passivated Cu films with an activation energy of 0.75 eV.