Material integration for the formation of advanced silicon-on-insulator materials by wafer bonding and etch-back will be discussed. Wafer bonding allows combining materials that may not be possible to grow on top of each other by any other technique. In our experiments, polycrystalline diamond, aluminum nitride or aluminum oxide films with thickness of 0.1-5 µm were deposited on silicon wafers. Bonding experiments were made with these films to bare silicon wafers with the goal of forming silicon-on-insulator structures with buried films of polycrystalline diamond, aluminum nitride or aluminum oxide. These silicon-on-insulator structures were aimed to address self-heating effects in conventional silicon-on-insulator materials with buried layers of silicon dioxide. The surfaces of the deposited diamond films were, by order of magnitude, too rough to allow direct bonding to a silicon wafer. In contrast the deposited aluminum nitride and aluminum oxide films did allow direct bonding to silicon. Bonding of the diamond surface to silicon was instead made through a deposited and polished layer of polycrystalline silicon on top of the diamond. In the case of the aluminum nitride electrostatic bonding was also demonstrated. Further, the compatibility of these insulators to silicon process technology was investigated.

Conformal epitaxy is an epitaxial growth technique capable of yielding low dislocation density III-V films on Silicon. In this technique, the growth of the III-V material occurs parallel to the silicon substrate, from the edge of a previously deposited III-V seed, the vertical growth being stopped by an overhanging capping layer. As an example, conformal GaAs layers on Silicon, presenting dislocation densities below 105cm−2, have been obtained using selective vapor phase epitaxy. These layers have then been used as high quality GaAs on Si substrates for subsequent vertical MBE regrowth of active structures. In this paper, we report on the integration of surface-emitting microcavity LEDs with their silicon drivers using this conformal growth technique. The global technology concept and the design of the active structures are first presented. The compatibility of the conformal growth technique with CMOS technology is then checked: the impact of the integration process on the performances of the drivers is for example quantified. Characterisations of the high crystalline quality of the conformal layers and of the LEDs structures grown on it are then shown. The electro-optical characteristics of the LEDs on Si are finally compared to those of reference LEDs on GaAs substrates in order to prove the efficiency of the integration procedure.

GaAs1–xPx (0.2 <; x < 0.7) was grown by metalorganic molecular beam epitaxy with a GaP buffer layer on Si for visible light-emitting devices. Insertion of the GaP buffer layer resulted in bright photoluminescence of the GaAsP epilayer. Pre-treatment of the Si substrate to avoid SiC formation was also critical to obtain good crystallinity of GaAsP. Dislocation formation, microstructure and photoluminescence in GaAsP grown layer are described. A GaAsP pn junction fabricated on GaP emitted visible light (˜1.86 eV). An initial GaAsP pn diode fabricated on Si emitted infrared light.

Single crystal Gd2O3 dielectric thin films were epitaxially grown on GaAs. The Gd2O3 film has a cubic structure isomorphic to Mn2O3, and is (110) oriented in single domain on the (100) GaAs surface. The oxide film has low leakage current densities ˜ 10–9 – 10–10 A/cmT2 at zero bias. Typical breakdown field is 4 MV/cm for an oxide film 185 Å thick, and >10 MV/cm for an oxide less than 50 Å thick. Both accumulation and inversion layers were observed in the Gd2O3-GaAs metal oxide semiconductor (MOS) diodes using capacitance-voltage (C-V) measurements, with an interfacial density of states around 1011 cm–2 eV–1.

Integrated planar circulator circuits operating at frequencies near 10 GHz have been fabricated using transferred film techniques. A 100 micrometer thick film of single-crystal yttrium iron garnet was transferred onto a metallized silicon die using a bond and lap-back process. The alloy bond layer was formed through a low-temperature solid-liquid interdiffusion process using films of indium and gold. This bond layer proved of sufficient strength to permit removal of the gadolinium gallium garnet substrate through grinding, but chemical analysis of the bond shows that interdiffusion occurs between the bond and metallization layers. These integrated gamet/silicon circulator circuits show good device performance.

Interface reinforcement brought about by addition of a γ-amino-propyl-triethoxy-silane (γ-APS) adhesion promoter layer between a silicon wafer and a spun-on benzocyclobutene polymer (BCB) is investigated. Combining cross-sectional TEM and XPS, crack growth is shown to occur along the γ-APS/BCB interface. Ion etching and in-situ XPS are further employed to study chain orientation and chemical bonding variations through the silane layer. A tendency of the amide group to orient away from the wafer is documented and Si-O-Si siloxane bonding at the γ- APS/SiO2 interface is hypothesized as an important mechanism for adhesion strength enhancement.

The reliability of press-packed IGBTs strongly depends on the solutions adopted in terms of heat dissipation and thermo-mechanical stress management so as to guarantee satisfactory electrical and thermal contact conditions throughout the service life. In this paper, two aspects concerning the design process of a single-chip press-pack IGBT are outlined: i) cyclic stresses and strains occurring in the package and in the chip are discussed on the basis of finite element (FE) simulations, ii) a testing rig developed for accelerated testing of single IGBT chips under controlled contact pressure conditions is presented.

Oxidation of layers of high-Al-content III-V materials by water vapor has become the enabling process for high-efficiency vertical cavity surface emitting lasers (VCSELs) and has potential applications for reducing substrate current leakage in GaAs-on-insulator (GOI) MESFETs. Because of the established importance of wet oxidation in optoelectronic devices and its potential applications in electronic devices, it has become increasingly important to understand the mechanism of wet oxidation and how it might be expected to affect both the fabrication and subsequent operation of devices that have been made using this technique. The mechanism of wet oxidation and the consequence of this mechanism for heterostructure design and ultimate device operation are discussed here.

Fabrication of high performance III-V devices and integrated circuits depends on careful control of layer thicknesses and compositions in the as-grown epitaxial layers and in the etching of these layers. The relatively high value of compound semiconductor devices (compared with high-volume Si devices) makes the use of advanced process control (with expensive in situ sensors) potentially advantageous. Considerable attention has been given to the problems of realtime feedback control of MBE growth systems. In this paper, I will discuss experiences with use of both in situ and ex situ monitors for controlling reactive ion etching (RIE) of III-V materials. Specific examples from an electron cyclotron resonance (ECR) RIE base contact etch from an AlInAs/GalnAs HBT process will be given. The relative merits of reflection-based wafer sensors vs. process state sensors (optical emission spectroscopy and mass spectroscopy) will be discussed. The unique opportunities and problems associated with the III-V materials and required etch processes will be contrasted to implementation of advanced wafer state endpoint detection schemes in Si and flat panel display processes. Specific problems and solutions from our research which I will discuss include chamber seasoning effects on the drift of optical emission based endpoint detection schemes and signal processing techniques for accounting for this drift, modeling of the optical dielectric function of the compounds of interest vs. composition, and the effects of surface roughness on optical thickness measurements.

Etching of a GaAs/Al0.3Ga0.7As/GaAs heterostructure in a nonselective etch solution of 25:1:75 (citric acid: H2O2:H2O) was studied in-situ using real time spectroscopic ellipsometry (RTSE). Etch rates for GaAs and AIGaAs of 15.3 nm/min and 17.6 nm/min, respectively, were determined by numerically fitting RTSE data. RTSE was successfully used to stop the etch after removal of the thin GaAs cap, while removing very little of the underlying AlGaAs layer. In addition, etch depth into the AIGaAs layer was accurately controlled, using RTSE to stop the etch with 100 nm remaining. Finally, RTSE data for wet etching of a patterned sample (75% coverage with photoresist) showed similar behavior to that for the unpattemed sample.

Surface science analysis can be utilized for improving the preparation of hetero-interfaces. Epitaxial InP(100)-films were prepared with TBP (tertiarybutylphosphine) and TMin (trimethylindium) as precursors in a commercial MOCVD apparatus. With a new type of transfer system the sample is shifted from the MOCVD apparatus to a UHV chamber within 20 s. A description of the new transfer system is given. RAS (reflection anisotropy spectroscopy) is carried out in the MOCVD and UHV environments. It shows whether the InP(100) surface corresponds to the (2×1) or (2×4) reconstruction or whether it is oxidized. For the first time contamination-free transfer of the (2×1) reconstructed, P-rich InP(100) surface is achieved.

We present the first report of the preparation and characterization of α-AIN films using reactive magnetron sputtering at cryogenic temperature. By comparison, analogous films grown at room temperature were polycrystalline. The films were characterized using X-ray Diffraction (XRD), Scanning Electron Microscopy (SEM), Rutherford Backscattering Spectrometry (RBS), Infrared (IR) Spectroscopy and optical transmission. XRD studies on films grown at room temperature showed diffraction peaks corresponding to (100), (101), (102) and (210) planes. In contrast, no peaks were observed for AIN films formed at liquid nitrogen temperature confirming the amorphous nature of the films. Composition analysis using RBS showed the presence of Al and N in ˜1:1 stoichiometry. The films were highly transparent and the computed bandgaps of αand c-AIN films were 5.90 and 5.89 eV respectively. We also consider the possibilities of wet etching the AIN films in diluted KOH solution and the results are discussed.

The pronounced segregation phenomenon in the distribution of p-type dopants Zn and Be in GaAs and related III-V compound heterostructures has been explained quantitatively by treating simultaneously the processes of dopant atom diffusion, segregation, and the effect of heterojunction carrier concentrations on these two aspects. Segregation of a dopant species between two semiconductor heterostructure layers is described by a model incorporating (i) a chemical effect on the neutral species; and (ii) in addition, a Fermi-level effect on the ionized species. The process of Zn and Be diffusion in GaAs and related compounds is governed by the doubly-positively-charged group III element self-interstitials whose thermal equilibrium concentration and hence also the Zn and Be diffusivities exhibit also a Fermi-level dependence, i.e., in proportion to p2.A heterojunction is consisting of a space charge region with an electric field, in which the hole concentration is different from those in the bulk layers. This influences the junction region concentrations of and of Zn− or Be−, which in turn influence the distribution of the ionized acceptor atoms. The overall process involves diffusion and segregation of holes, , Zn− or Be−, and an ionized interstitial acceptor species. The junction electric field also changes with time and position.

We have investigated the peak voltage (Vp) in InAs/A1Sb/GaSb/A1Sb/InAs double-barrier resonant interband tunneling (DBRIT) diodes with various GaSb well widths (Lw). After eliminating the voltage drop resulting from parasitic resistance included in the measured peak voltage (Vpm), we found that the intrinsic peak voltage (Vpint) was almost insensitive to Lw and had a small, and virtually constant value (∼ 60 mV) at Lw, ranging from 10 to 30 monolayers. This insensitivity contrasts with the peak voltage of the conventional resonant tunneling diodes with intraband tunneling, which is sensitive to changes in Lw. This insensitivity can be explained by the fact that Vpint in Sb-based BDRIT diodes is affected by the occupied states in the collector rather than by the resonance level itself in the interband tunneling process.

We present the studies of the thermal stability of various metal including Au, Ti, Pt, Pd and Pt/Ti/Pt/Au Schottky contacts on strained Ga0.2In0.8P/InP semiconductors. Auger electron spectroscopy (AES) analysis and cross-sectional TEM of the thermally annealed Schottky diode were performed to investigate the failure mechanism. For Pt/Ti/Pt/Au schottky contacts on strained GalnP/InP, no significant change was found for samples annealed up to 350°C. However, a drastic degradation of the barrier height and the ideality factor was observed in samples annealed at 400°C, which may be caused by the interdiffusion and penetration of metals into the semiconductor. Finally InGaAs/InP doped channel heterojunction FET's (DC-HFET's) with a GaInP Schottky barrier enhancement layer (SBEL) were grown and fabricated. The 0.25 μm gate-length devices showed excellent DC and RF performance, with anfi of 117 GHz and an fmax of 168 GHz.

AlGaAs/GaAs based high electron mobility transistors (HEMTs) with Cu/Ti metallized gates have been fabricated. Copper gates were used to achieve low gate resistance and to minimize the hydrogen induced device degradation. The DC measurement of the processed AlGaAs/GaAs HEMTs with Cu/Ti gates shows comparable performance to similar Au based GaAs HEMTs. The Cu-based HEMTs were also subjected to elevated temperature testing under 5% H2 –N2 forming gas up to 250°C and 8 hours and no degradation due to hydrogen effects was found.

Effects of CF4 reactive ion etching on electrical characteristics of Si-doped Al0.2Ga0.8As layers were studied with capacitance-voltage and deep level transient spectroscopy measurements. Plasma exposure for about 30 s drastically degrades the electrical characteristics. Post-annealing at 360 °C for 20 s partially recovers the carrier concentrations. After the post-annealing, some electron traps were observed. Two of the traps show bi-stability. The concentrations of the two traps increase with forward bias temperature annealing and decrease with reverse bias temperature annealing.

We have fabricated n-channel InSb MISFETs using SiO2 films as gate insulators. The insulator was deposited by PECVD using tetra-isocyanate-silane (TICS) and oxygen (O2) as source gases. Threshold voltage and carrier mobility at 77K were 0.5V and 4200cm2/Vs, respectively.

This paper will summarize the technology tradeoffs that are involved in the implementation of high-speed integrated circuit technology for communications applications. The advantages of Si/SiGe and III-V technology with respect to CMOS and Si bipolar technologies are discussed.

We grew Si1−x, Gex / Si / Si1−xGex heterostructures with abrupt interfaces for a high-speed device application. In order to eliminate the interface and the impurity scatterings, a two-stepsolid-phase epitaxy (SPE) was developed newly. This SPE can obtain an abrupt interface between the upper Si1−xGex. and the Si-channel layers as well as a sharp Sb-doping profile in the upper Si1−xGex layer. Single-step SPE growth of the Si1−xGex. layer including the Sb-doped layer caused solid state diffusion of Sb and made the doping-profile difficult to control. A two-step SPE, (that is, two independent SPE processes forming the Si1−xGex. and the Sb-doped layers), obtained a sharp Sb depth profile and high electrical activation in the Sb-doped Si1−xGex. layer. However, the number of modulation-doped carriers in the Si channel layer was small. Calculation of the carrier distribution between the channel and the doped layer suggests that the carrier density in the channel is low when the Sb-doping profile is extremely sharp; thus, precise control of the modulation-doped-carrier density by optimizing the thickness of the Sb-doped layer is crucial for operating modulation-doped field-effect transistors (MODFETs).