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Two-step Defect Reduction of GaAs/Si Epitaxy by Selective Aspect Ratio Trapping

Published online by Cambridge University Press:  01 February 2011

Jizhong Li ,
J. Bai ,
C. Major ,
M. Carroll ,
A. Lochtefeld  and
Z. Shellenbarger
Jizhong Li
Affiliation:
[email protected], Amberwave, R&D, 13 Garabedian Dr, Salem, NH, 03079, United States, 603-870-8675, 603-870-8608
J. Bai
Affiliation:
[email protected], Amberwave, R&D, 13 Garabedian Drive, Salem, NH, 03079, United States
C. Major
Affiliation:
[email protected], Amberwave, Ops, 13 Garabedian Drive, Salem, NH, 03079, United States
M. Carroll
Affiliation:
[email protected], Amberwave, R&D, 13 Garabedian Drive, Salem, NH, 03079, United States
A. Lochtefeld
Affiliation:
[email protected], Amberwave, R&D, 13 Garabedian Drive, Salem, NH, 03079, United States
Z. Shellenbarger
Affiliation:
[email protected], Sarnoff, Optoelectronics, 201 Washington Rd, Princeton, NJ, 08543, United States
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Abstract

We report on the MOCVD growth of GaAs on patterned Si utilizing the Aspect Ratio Trapping (ART) method to reduce threading dislocations resulting from lattice mismatch. Defect-free GaAs was obtained from growth in sub-micron trenches formed in SiO2 on Si (001) substrates. Material quality has been characterized by cross-sectional and plan-view TEM and XRD. It was found that when growing GaAs above the trenched region, coalescence-induced threading dislocations (TDs) and planar defects were introduced at the coalescence junction interfaces. These defects were found to be unrelated to the misfit defects (MDs) on GaAs/Si interface that originated during initial epitaxial growth. Causes of coalescence defect formation were experimentally investigated by employing a two-step defect reduction scheme. It is concluded that by further optimizing growth conditions during coalesce layer growth, low defect-density GaAs material can be obtained on Si substrate.

Keywords

epitaxydefectsdislocations
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1030: Symposium G – Large-Area Processing and Patterning for Active Optical and Electronic Devices , 2007 , 1030-G06-17
Copyright
Copyright © Materials Research Society 2008

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