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Surface States at LT GaAs-n+ GaAs Interfaces

Published online by Cambridge University Press:  25 February 2011

Ashlsh K. Verma ,
J. S. Smith  and
Eicke R. Weber
Ashlsh K. Verma
Affiliation:
Department of Electrical Engineering, University of California, Berkeley, CA 94720.
J. S. Smith
Affiliation:
Department of Electrical Engineering, University of California, Berkeley, CA 94720.
Eicke R. Weber
Affiliation:
Department of Material Science, University of California, Berkeley, CA 94720.
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Extract

GaAs grown using Molecular Beam Epitaxy at below normal substrate temperatures (∼ 220 °C) has found many potential applications in GaAs MESFET devices. These so-called Low Temperature (LT) layers were originally used between the MESFET substrate and active region to eliminate backgating effects.[1] More recently, LT layers have been incorporated into MESFET gate structures to improve gate breakdown characteristics.[2] [3] When used in this capacity, the quality of the LT GaAs - n+ GaAs interface becomes an important issue: a large number of traps at the interface will result in channel mobility degradation. Furthermore, it is desirable to develop a method by which the interface quality can be evaluated through simple electrical measurements.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 281: Symposium D – Semiconductor Heterostructures for Photonic and Electronic Applications , 1992 , 85
Copyright
Copyright © Materials Research Society 1993

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References

REFERENCES

1. Smith, F. W., Calawa, A. R., Chen, C.-L., Manfra, M.J. and Mahoney, L.J., IEEE Electron Device Lett. 9, 77 (1988).Google Scholar
2. Yin, L.-W., Hwang, Y., Lee, J.H., Kolbas, R.M., Trew, R.J. and Mishra, U.K., IEEE Electron Device Lett. 11, 561 (1990).Google Scholar
3. Chen, C.-L., Smith, F.W., Clifton, B.J., Mahoney, L.J., Manfra, M.J. and Calawa, A.R., IEEE Electron Device Lett. 12, 306 (1991).Google Scholar
4. Nicollian, E.H. and Goetzenberger, A., Bell System Tech. J. 46, 1055 (1967).Google Scholar
5. Sze, S.M., Physics of Semiconductor Devices. 2nd ed. (J. Wiley, New York, 1981).Google Scholar
6. Manasreh, M.O., Look, D.C., Evans, K.R. and Stutz, C.E., Phys. Rev. B 41, 10272 (1990).Google Scholar
7. Shinoda, Y. and Kobayashi, T., J. Applied Physics 52, 6386 (1981).Google Scholar